| hwprobe.h (0ad70db5eb21e50ed693fa274bea0346de453e29) | hwprobe.h (fc078ea317cc856c1e82997da7e8fd4d6da7aa29) |
|---|---|
| 1/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2/* 3 * Copyright 2023 Rivos, Inc 4 */ 5 6#ifndef _UAPI_ASM_HWPROBE_H 7#define _UAPI_ASM_HWPROBE_H 8 --- 56 unchanged lines hidden (view full) --- 65#define RISCV_HWPROBE_EXT_ZVE64X (1ULL << 39) 66#define RISCV_HWPROBE_EXT_ZVE64F (1ULL << 40) 67#define RISCV_HWPROBE_EXT_ZVE64D (1ULL << 41) 68#define RISCV_HWPROBE_EXT_ZIMOP (1ULL << 42) 69#define RISCV_HWPROBE_EXT_ZCA (1ULL << 43) 70#define RISCV_HWPROBE_EXT_ZCB (1ULL << 44) 71#define RISCV_HWPROBE_EXT_ZCD (1ULL << 45) 72#define RISCV_HWPROBE_EXT_ZCF (1ULL << 46) | 1/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2/* 3 * Copyright 2023 Rivos, Inc 4 */ 5 6#ifndef _UAPI_ASM_HWPROBE_H 7#define _UAPI_ASM_HWPROBE_H 8 --- 56 unchanged lines hidden (view full) --- 65#define RISCV_HWPROBE_EXT_ZVE64X (1ULL << 39) 66#define RISCV_HWPROBE_EXT_ZVE64F (1ULL << 40) 67#define RISCV_HWPROBE_EXT_ZVE64D (1ULL << 41) 68#define RISCV_HWPROBE_EXT_ZIMOP (1ULL << 42) 69#define RISCV_HWPROBE_EXT_ZCA (1ULL << 43) 70#define RISCV_HWPROBE_EXT_ZCB (1ULL << 44) 71#define RISCV_HWPROBE_EXT_ZCD (1ULL << 45) 72#define RISCV_HWPROBE_EXT_ZCF (1ULL << 46) |
| 73#define RISCV_HWPROBE_EXT_ZCMOP (1ULL << 47) |
|
| 73#define RISCV_HWPROBE_KEY_CPUPERF_0 5 74#define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) 75#define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) 76#define RISCV_HWPROBE_MISALIGNED_SLOW (2 << 0) 77#define RISCV_HWPROBE_MISALIGNED_FAST (3 << 0) 78#define RISCV_HWPROBE_MISALIGNED_UNSUPPORTED (4 << 0) 79#define RISCV_HWPROBE_MISALIGNED_MASK (7 << 0) 80#define RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE 6 81/* Increase RISCV_HWPROBE_MAX_KEY when adding items. */ 82 83/* Flags */ 84#define RISCV_HWPROBE_WHICH_CPUS (1 << 0) 85 86#endif | 74#define RISCV_HWPROBE_KEY_CPUPERF_0 5 75#define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) 76#define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) 77#define RISCV_HWPROBE_MISALIGNED_SLOW (2 << 0) 78#define RISCV_HWPROBE_MISALIGNED_FAST (3 << 0) 79#define RISCV_HWPROBE_MISALIGNED_UNSUPPORTED (4 << 0) 80#define RISCV_HWPROBE_MISALIGNED_MASK (7 << 0) 81#define RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE 6 82/* Increase RISCV_HWPROBE_MAX_KEY when adding items. */ 83 84/* Flags */ 85#define RISCV_HWPROBE_WHICH_CPUS (1 << 0) 86 87#endif |