vector.h (36ec807b627b4c0a0a382f0ae48eac7187d14b2b) vector.h (d1703dc7bc8ec7adb91f5ceaf1556ff1ed212858)
1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Copyright (C) 2020 SiFive
4 */
5
6#ifndef __ASM_RISCV_VECTOR_H
7#define __ASM_RISCV_VECTOR_H
8

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16#include <linux/sched/task_stack.h>
17#include <asm/ptrace.h>
18#include <asm/cpufeature.h>
19#include <asm/csr.h>
20#include <asm/asm.h>
21
22extern unsigned long riscv_v_vsize;
23int riscv_v_setup_vsize(void);
1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Copyright (C) 2020 SiFive
4 */
5
6#ifndef __ASM_RISCV_VECTOR_H
7#define __ASM_RISCV_VECTOR_H
8

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16#include <linux/sched/task_stack.h>
17#include <asm/ptrace.h>
18#include <asm/cpufeature.h>
19#include <asm/csr.h>
20#include <asm/asm.h>
21
22extern unsigned long riscv_v_vsize;
23int riscv_v_setup_vsize(void);
24bool insn_is_vector(u32 insn_buf);
24bool riscv_v_first_use_handler(struct pt_regs *regs);
25void kernel_vector_begin(void);
26void kernel_vector_end(void);
27void get_cpu_vector_context(void);
28void put_cpu_vector_context(void);
29void riscv_v_thread_free(struct task_struct *tsk);
30void __init riscv_v_setup_ctx_cache(void);
31void riscv_v_thread_alloc(struct task_struct *tsk);

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263bool riscv_v_vstate_ctrl_user_allowed(void);
264
265#else /* ! CONFIG_RISCV_ISA_V */
266
267struct pt_regs;
268
269static inline int riscv_v_setup_vsize(void) { return -EOPNOTSUPP; }
270static __always_inline bool has_vector(void) { return false; }
25bool riscv_v_first_use_handler(struct pt_regs *regs);
26void kernel_vector_begin(void);
27void kernel_vector_end(void);
28void get_cpu_vector_context(void);
29void put_cpu_vector_context(void);
30void riscv_v_thread_free(struct task_struct *tsk);
31void __init riscv_v_setup_ctx_cache(void);
32void riscv_v_thread_alloc(struct task_struct *tsk);

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264bool riscv_v_vstate_ctrl_user_allowed(void);
265
266#else /* ! CONFIG_RISCV_ISA_V */
267
268struct pt_regs;
269
270static inline int riscv_v_setup_vsize(void) { return -EOPNOTSUPP; }
271static __always_inline bool has_vector(void) { return false; }
272static __always_inline bool insn_is_vector(u32 insn_buf) { return false; }
271static inline bool riscv_v_first_use_handler(struct pt_regs *regs) { return false; }
272static inline bool riscv_v_vstate_query(struct pt_regs *regs) { return false; }
273static inline bool riscv_v_vstate_ctrl_user_allowed(void) { return false; }
274#define riscv_v_vsize (0)
275#define riscv_v_vstate_discard(regs) do {} while (0)
276#define riscv_v_vstate_save(vstate, regs) do {} while (0)
277#define riscv_v_vstate_restore(vstate, regs) do {} while (0)
278#define __switch_to_vector(__prev, __next) do {} while (0)

--- 20 unchanged lines hidden --- 		273static inline bool riscv_v_first_use_handler(struct pt_regs *regs) { return false; }
274static inline bool riscv_v_vstate_query(struct pt_regs *regs) { return false; }
275static inline bool riscv_v_vstate_ctrl_user_allowed(void) { return false; }
276#define riscv_v_vsize (0)
277#define riscv_v_vstate_discard(regs) do {} while (0)
278#define riscv_v_vstate_save(vstate, regs) do {} while (0)
279#define riscv_v_vstate_restore(vstate, regs) do {} while (0)
280#define __switch_to_vector(__prev, __next) do {} while (0)

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