insn.h (642073c306e66daca108cb630d169129e50a6ba3) insn.h (af0ead42f69389cd4ed68e1a4c6cde45c0adb35c)
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2020 SiFive
4 */
5
6#ifndef _ASM_RISCV_INSN_H
7#define _ASM_RISCV_INSN_H
8

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58#define RV_B_IMM_10_5_MASK GENMASK(5, 0)
59#define RV_B_IMM_4_1_MASK GENMASK(3, 0)
60#define RV_B_IMM_11_MASK GENMASK(0, 0)
61
62/* The register offset in RVG instruction */
63#define RVG_RS1_OPOFF 15
64#define RVG_RS2_OPOFF 20
65#define RVG_RD_OPOFF 7
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2020 SiFive
4 */
5
6#ifndef _ASM_RISCV_INSN_H
7#define _ASM_RISCV_INSN_H
8

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58#define RV_B_IMM_10_5_MASK GENMASK(5, 0)
59#define RV_B_IMM_4_1_MASK GENMASK(3, 0)
60#define RV_B_IMM_11_MASK GENMASK(0, 0)
61
62/* The register offset in RVG instruction */
63#define RVG_RS1_OPOFF 15
64#define RVG_RS2_OPOFF 20
65#define RVG_RD_OPOFF 7
66#define RVG_RS1_MASK GENMASK(4, 0)
66#define RVG_RD_MASK GENMASK(4, 0)
67
68/* The bit field of immediate value in RVC J instruction */
69#define RVC_J_IMM_SIGN_OPOFF 12
70#define RVC_J_IMM_4_OPOFF 11
71#define RVC_J_IMM_9_8_OPOFF 9
72#define RVC_J_IMM_10_OPOFF 8
73#define RVC_J_IMM_6_OPOFF 7

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105#define RVC_B_IMM_7_6_MASK GENMASK(1, 0)
106#define RVC_B_IMM_2_1_MASK GENMASK(1, 0)
107#define RVC_B_IMM_5_MASK GENMASK(0, 0)
108
109#define RVC_INSN_FUNCT4_MASK GENMASK(15, 12)
110#define RVC_INSN_FUNCT4_OPOFF 12
111#define RVC_INSN_FUNCT3_MASK GENMASK(15, 13)
112#define RVC_INSN_FUNCT3_OPOFF 13
67#define RVG_RD_MASK GENMASK(4, 0)
68
69/* The bit field of immediate value in RVC J instruction */
70#define RVC_J_IMM_SIGN_OPOFF 12
71#define RVC_J_IMM_4_OPOFF 11
72#define RVC_J_IMM_9_8_OPOFF 9
73#define RVC_J_IMM_10_OPOFF 8
74#define RVC_J_IMM_6_OPOFF 7

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106#define RVC_B_IMM_7_6_MASK GENMASK(1, 0)
107#define RVC_B_IMM_2_1_MASK GENMASK(1, 0)
108#define RVC_B_IMM_5_MASK GENMASK(0, 0)
109
110#define RVC_INSN_FUNCT4_MASK GENMASK(15, 12)
111#define RVC_INSN_FUNCT4_OPOFF 12
112#define RVC_INSN_FUNCT3_MASK GENMASK(15, 13)
113#define RVC_INSN_FUNCT3_OPOFF 13
113#define RVC_INSN_J_RS1_MASK GENMASK(11, 7)
114#define RVC_INSN_J_RS2_MASK GENMASK(6, 2)
115#define RVC_INSN_OPCODE_MASK GENMASK(1, 0)
116#define RVC_ENCODE_FUNCT3(f_) (RVC_FUNCT3_##f_ << RVC_INSN_FUNCT3_OPOFF)
117#define RVC_ENCODE_FUNCT4(f_) (RVC_FUNCT4_##f_ << RVC_INSN_FUNCT4_OPOFF)
118
119/* The register offset in RVC op=C0 instruction */
120#define RVC_C0_RS1_OPOFF 7
121#define RVC_C0_RS2_OPOFF 2
122#define RVC_C0_RD_OPOFF 2
123
124/* The register offset in RVC op=C1 instruction */
125#define RVC_C1_RS1_OPOFF 7
126#define RVC_C1_RS2_OPOFF 2
127#define RVC_C1_RD_OPOFF 7
128
129/* The register offset in RVC op=C2 instruction */
130#define RVC_C2_RS1_OPOFF 7
131#define RVC_C2_RS2_OPOFF 2
132#define RVC_C2_RD_OPOFF 7
114#define RVC_INSN_J_RS2_MASK GENMASK(6, 2)
115#define RVC_INSN_OPCODE_MASK GENMASK(1, 0)
116#define RVC_ENCODE_FUNCT3(f_) (RVC_FUNCT3_##f_ << RVC_INSN_FUNCT3_OPOFF)
117#define RVC_ENCODE_FUNCT4(f_) (RVC_FUNCT4_##f_ << RVC_INSN_FUNCT4_OPOFF)
118
119/* The register offset in RVC op=C0 instruction */
120#define RVC_C0_RS1_OPOFF 7
121#define RVC_C0_RS2_OPOFF 2
122#define RVC_C0_RD_OPOFF 2
123
124/* The register offset in RVC op=C1 instruction */
125#define RVC_C1_RS1_OPOFF 7
126#define RVC_C1_RS2_OPOFF 2
127#define RVC_C1_RD_OPOFF 7
128
129/* The register offset in RVC op=C2 instruction */
130#define RVC_C2_RS1_OPOFF 7
131#define RVC_C2_RS2_OPOFF 2
132#define RVC_C2_RD_OPOFF 7
133#define RVC_C2_RS1_MASK GENMASK(4, 0)
133
134/* parts of opcode for RVG*/
135#define RVG_OPCODE_FENCE 0x0f
136#define RVG_OPCODE_AUIPC 0x17
137#define RVG_OPCODE_BRANCH 0x63
138#define RVG_OPCODE_JALR 0x67
139#define RVG_OPCODE_JAL 0x6f
140#define RVG_OPCODE_SYSTEM 0x73

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241/* C.JAL is an RV32C-only instruction */
242__RISCV_INSN_FUNCS(c_jal, RVC_MASK_C_JAL, RVC_MATCH_C_JAL)
243#else
244#define riscv_insn_is_c_jal(opcode) 0
245#endif
246__RISCV_INSN_FUNCS(auipc, RVG_MASK_AUIPC, RVG_MATCH_AUIPC)
247__RISCV_INSN_FUNCS(jalr, RVG_MASK_JALR, RVG_MATCH_JALR)
248__RISCV_INSN_FUNCS(jal, RVG_MASK_JAL, RVG_MATCH_JAL)
134
135/* parts of opcode for RVG*/
136#define RVG_OPCODE_FENCE 0x0f
137#define RVG_OPCODE_AUIPC 0x17
138#define RVG_OPCODE_BRANCH 0x63
139#define RVG_OPCODE_JALR 0x67
140#define RVG_OPCODE_JAL 0x6f
141#define RVG_OPCODE_SYSTEM 0x73

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242/* C.JAL is an RV32C-only instruction */
243__RISCV_INSN_FUNCS(c_jal, RVC_MASK_C_JAL, RVC_MATCH_C_JAL)
244#else
245#define riscv_insn_is_c_jal(opcode) 0
246#endif
247__RISCV_INSN_FUNCS(auipc, RVG_MASK_AUIPC, RVG_MATCH_AUIPC)
248__RISCV_INSN_FUNCS(jalr, RVG_MASK_JALR, RVG_MATCH_JALR)
249__RISCV_INSN_FUNCS(jal, RVG_MASK_JAL, RVG_MATCH_JAL)
250__RISCV_INSN_FUNCS(c_jr, RVC_MASK_C_JR, RVC_MATCH_C_JR)
251__RISCV_INSN_FUNCS(c_jalr, RVC_MASK_C_JALR, RVC_MATCH_C_JALR)
249__RISCV_INSN_FUNCS(c_j, RVC_MASK_C_J, RVC_MATCH_C_J)
250__RISCV_INSN_FUNCS(beq, RVG_MASK_BEQ, RVG_MATCH_BEQ)
251__RISCV_INSN_FUNCS(bne, RVG_MASK_BNE, RVG_MATCH_BNE)
252__RISCV_INSN_FUNCS(blt, RVG_MASK_BLT, RVG_MATCH_BLT)
253__RISCV_INSN_FUNCS(bge, RVG_MASK_BGE, RVG_MATCH_BGE)
254__RISCV_INSN_FUNCS(bltu, RVG_MASK_BLTU, RVG_MATCH_BLTU)
255__RISCV_INSN_FUNCS(bgeu, RVG_MASK_BGEU, RVG_MATCH_BGEU)
256__RISCV_INSN_FUNCS(c_beqz, RVC_MASK_C_BEQZ, RVC_MATCH_C_BEQZ)

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267}
268
269/* special case to catch _any_ branch instruction */
270static __always_inline bool riscv_insn_is_branch(u32 code)
271{
272 return (code & RV_INSN_OPCODE_MASK) == RVG_OPCODE_BRANCH;
273}
274
252__RISCV_INSN_FUNCS(c_j, RVC_MASK_C_J, RVC_MATCH_C_J)
253__RISCV_INSN_FUNCS(beq, RVG_MASK_BEQ, RVG_MATCH_BEQ)
254__RISCV_INSN_FUNCS(bne, RVG_MASK_BNE, RVG_MATCH_BNE)
255__RISCV_INSN_FUNCS(blt, RVG_MASK_BLT, RVG_MATCH_BLT)
256__RISCV_INSN_FUNCS(bge, RVG_MASK_BGE, RVG_MATCH_BGE)
257__RISCV_INSN_FUNCS(bltu, RVG_MASK_BLTU, RVG_MATCH_BLTU)
258__RISCV_INSN_FUNCS(bgeu, RVG_MASK_BGEU, RVG_MATCH_BGEU)
259__RISCV_INSN_FUNCS(c_beqz, RVC_MASK_C_BEQZ, RVC_MATCH_C_BEQZ)

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270}
271
272/* special case to catch _any_ branch instruction */
273static __always_inline bool riscv_insn_is_branch(u32 code)
274{
275 return (code & RV_INSN_OPCODE_MASK) == RVG_OPCODE_BRANCH;
276}
277
275static __always_inline bool riscv_insn_is_c_jr(u32 code)
276{
277 return (code & RVC_MASK_C_JR) == RVC_MATCH_C_JR &&
278 (code & RVC_INSN_J_RS1_MASK) != 0;
279}
280
281static __always_inline bool riscv_insn_is_c_jalr(u32 code)
282{
283 return (code & RVC_MASK_C_JALR) == RVC_MATCH_C_JALR &&
284 (code & RVC_INSN_J_RS1_MASK) != 0;
285}
286
287#define RV_IMM_SIGN(x) (-(((x) >> 31) & 1))
288#define RVC_IMM_SIGN(x) (-(((x) >> 12) & 1))
289#define RV_X(X, s, mask) (((X) >> (s)) & (mask))
290#define RVC_X(X, s, mask) RV_X(X, s, mask)
291
278#define RV_IMM_SIGN(x) (-(((x) >> 31) & 1))
279#define RVC_IMM_SIGN(x) (-(((x) >> 12) & 1))
280#define RV_X(X, s, mask) (((X) >> (s)) & (mask))
281#define RVC_X(X, s, mask) RV_X(X, s, mask)
282
283#define RV_EXTRACT_RS1_REG(x) \
284 ({typeof(x) x_ = (x); \
285 (RV_X(x_, RVG_RS1_OPOFF, RVG_RS1_MASK)); })
286
292#define RV_EXTRACT_RD_REG(x) \
293 ({typeof(x) x_ = (x); \
294 (RV_X(x_, RVG_RD_OPOFF, RVG_RD_MASK)); })
295
296#define RV_EXTRACT_UTYPE_IMM(x) \
297 ({typeof(x) x_ = (x); \
298 (RV_X(x_, RV_U_IMM_31_12_OPOFF, RV_U_IMM_31_12_MASK)); })
299

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311
312#define RV_EXTRACT_BTYPE_IMM(x) \
313 ({typeof(x) x_ = (x); \
314 (RV_X(x_, RV_B_IMM_4_1_OPOFF, RV_B_IMM_4_1_MASK) << RV_B_IMM_4_1_OFF) | \
315 (RV_X(x_, RV_B_IMM_10_5_OPOFF, RV_B_IMM_10_5_MASK) << RV_B_IMM_10_5_OFF) | \
316 (RV_X(x_, RV_B_IMM_11_OPOFF, RV_B_IMM_11_MASK) << RV_B_IMM_11_OFF) | \
317 (RV_IMM_SIGN(x_) << RV_B_IMM_SIGN_OFF); })
318
287#define RV_EXTRACT_RD_REG(x) \
288 ({typeof(x) x_ = (x); \
289 (RV_X(x_, RVG_RD_OPOFF, RVG_RD_MASK)); })
290
291#define RV_EXTRACT_UTYPE_IMM(x) \
292 ({typeof(x) x_ = (x); \
293 (RV_X(x_, RV_U_IMM_31_12_OPOFF, RV_U_IMM_31_12_MASK)); })
294

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306
307#define RV_EXTRACT_BTYPE_IMM(x) \
308 ({typeof(x) x_ = (x); \
309 (RV_X(x_, RV_B_IMM_4_1_OPOFF, RV_B_IMM_4_1_MASK) << RV_B_IMM_4_1_OFF) | \
310 (RV_X(x_, RV_B_IMM_10_5_OPOFF, RV_B_IMM_10_5_MASK) << RV_B_IMM_10_5_OFF) | \
311 (RV_X(x_, RV_B_IMM_11_OPOFF, RV_B_IMM_11_MASK) << RV_B_IMM_11_OFF) | \
312 (RV_IMM_SIGN(x_) << RV_B_IMM_SIGN_OFF); })
313
314#define RVC_EXTRACT_C2_RS1_REG(x) \
315 ({typeof(x) x_ = (x); \
316 (RV_X(x_, RVC_C2_RS1_OPOFF, RVC_C2_RS1_MASK)); })
317
319#define RVC_EXTRACT_JTYPE_IMM(x) \
320 ({typeof(x) x_ = (x); \
321 (RVC_X(x_, RVC_J_IMM_3_1_OPOFF, RVC_J_IMM_3_1_MASK) << RVC_J_IMM_3_1_OFF) | \
322 (RVC_X(x_, RVC_J_IMM_4_OPOFF, RVC_J_IMM_4_MASK) << RVC_J_IMM_4_OFF) | \
323 (RVC_X(x_, RVC_J_IMM_5_OPOFF, RVC_J_IMM_5_MASK) << RVC_J_IMM_5_OFF) | \
324 (RVC_X(x_, RVC_J_IMM_6_OPOFF, RVC_J_IMM_6_MASK) << RVC_J_IMM_6_OFF) | \
325 (RVC_X(x_, RVC_J_IMM_7_OPOFF, RVC_J_IMM_7_MASK) << RVC_J_IMM_7_OFF) | \
326 (RVC_X(x_, RVC_J_IMM_9_8_OPOFF, RVC_J_IMM_9_8_MASK) << RVC_J_IMM_9_8_OFF) | \

--- 95 unchanged lines hidden --- 		318#define RVC_EXTRACT_JTYPE_IMM(x) \
319 ({typeof(x) x_ = (x); \
320 (RVC_X(x_, RVC_J_IMM_3_1_OPOFF, RVC_J_IMM_3_1_MASK) << RVC_J_IMM_3_1_OFF) | \
321 (RVC_X(x_, RVC_J_IMM_4_OPOFF, RVC_J_IMM_4_MASK) << RVC_J_IMM_4_OFF) | \
322 (RVC_X(x_, RVC_J_IMM_5_OPOFF, RVC_J_IMM_5_MASK) << RVC_J_IMM_5_OFF) | \
323 (RVC_X(x_, RVC_J_IMM_6_OPOFF, RVC_J_IMM_6_MASK) << RVC_J_IMM_6_OFF) | \
324 (RVC_X(x_, RVC_J_IMM_7_OPOFF, RVC_J_IMM_7_MASK) << RVC_J_IMM_7_OFF) | \
325 (RVC_X(x_, RVC_J_IMM_9_8_OPOFF, RVC_J_IMM_9_8_MASK) << RVC_J_IMM_9_8_OFF) | \

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