hwcap.h (f83d9396d1f63048c423efa00e4e244da10a35fd) hwcap.h (1631ba1259d6d7f49b6028f2a1a0fa02be1c522a)
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copied from arch/arm64/include/asm/hwcap.h
4 *
5 * Copyright (C) 2012 ARM Ltd.
6 * Copyright (C) 2017 SiFive
7 */
8#ifndef _ASM_RISCV_HWCAP_H
9#define _ASM_RISCV_HWCAP_H
10
11#include <linux/bits.h>
12#include <uapi/asm/hwcap.h>
13
14#ifndef __ASSEMBLY__
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copied from arch/arm64/include/asm/hwcap.h
4 *
5 * Copyright (C) 2012 ARM Ltd.
6 * Copyright (C) 2017 SiFive
7 */
8#ifndef _ASM_RISCV_HWCAP_H
9#define _ASM_RISCV_HWCAP_H
10
11#include <linux/bits.h>
12#include <uapi/asm/hwcap.h>
13
14#ifndef __ASSEMBLY__
15#include <linux/jump_label.h>
15/*
16 * This yields a mask that user programs can use to figure out what
17 * instruction set this cpu supports.
18 */
19#define ELF_HWCAP (elf_hwcap)
20
21enum {
22 CAP_HWCAP = 1,

--- 25 unchanged lines hidden (view full) ---

48 * The logical ID should start from RISCV_ISA_EXT_BASE and must not exceed
49 * RISCV_ISA_EXT_MAX. 0-25 range is reserved for single letter
50 * extensions while all the multi-letter extensions should define the next
51 * available logical extension id.
52 */
53enum riscv_isa_ext_id {
54 RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE,
55 RISCV_ISA_EXT_SVPBMT,
16/*
17 * This yields a mask that user programs can use to figure out what
18 * instruction set this cpu supports.
19 */
20#define ELF_HWCAP (elf_hwcap)
21
22enum {
23 CAP_HWCAP = 1,

--- 25 unchanged lines hidden (view full) ---

49 * The logical ID should start from RISCV_ISA_EXT_BASE and must not exceed
50 * RISCV_ISA_EXT_MAX. 0-25 range is reserved for single letter
51 * extensions while all the multi-letter extensions should define the next
52 * available logical extension id.
53 */
54enum riscv_isa_ext_id {
55 RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE,
56 RISCV_ISA_EXT_SVPBMT,
57 RISCV_ISA_EXT_ZICBOM,
56 RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX,
57};
58
58 RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX,
59};
60
61/*
62 * This enum represents the logical ID for each RISC-V ISA extension static
63 * keys. We can use static key to optimize code path if some ISA extensions
64 * are available.
65 */
66enum riscv_isa_ext_key {
67 RISCV_ISA_EXT_KEY_FPU, /* For 'F' and 'D' */
68 RISCV_ISA_EXT_KEY_MAX,
69};
70
59struct riscv_isa_ext_data {
60 /* Name of the extension displayed to userspace via /proc/cpuinfo */
61 char uprop[RISCV_ISA_EXT_NAME_LEN_MAX];
62 /* The logical ISA extension ID */
63 unsigned int isa_ext_id;
64};
65
71struct riscv_isa_ext_data {
72 /* Name of the extension displayed to userspace via /proc/cpuinfo */
73 char uprop[RISCV_ISA_EXT_NAME_LEN_MAX];
74 /* The logical ISA extension ID */
75 unsigned int isa_ext_id;
76};
77
78extern struct static_key_false riscv_isa_ext_keys[RISCV_ISA_EXT_KEY_MAX];
79
80static __always_inline int riscv_isa_ext2key(int num)
81{
82 switch (num) {
83 case RISCV_ISA_EXT_f:
84 return RISCV_ISA_EXT_KEY_FPU;
85 case RISCV_ISA_EXT_d:
86 return RISCV_ISA_EXT_KEY_FPU;
87 default:
88 return -EINVAL;
89 }
90}
91
66unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap);
67
68#define riscv_isa_extension_mask(ext) BIT_MASK(RISCV_ISA_EXT_##ext)
69
70bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int bit);
71#define riscv_isa_extension_available(isa_bitmap, ext) \
72 __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_##ext)
73
74#endif
75
76#endif /* _ASM_RISCV_HWCAP_H */
92unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap);
93
94#define riscv_isa_extension_mask(ext) BIT_MASK(RISCV_ISA_EXT_##ext)
95
96bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int bit);
97#define riscv_isa_extension_available(isa_bitmap, ext) \
98 __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_##ext)
99
100#endif
101
102#endif /* _ASM_RISCV_HWCAP_H */