| hwcap.h (f557af081de6b45a25e27d633b4d8d2dbc2f428e) | hwcap.h (23c996fc2bc1978a02c64eddb90b4ab5d309c8df) |
|---|---|
| 1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Copied from arch/arm64/include/asm/hwcap.h 4 * 5 * Copyright (C) 2012 ARM Ltd. 6 * Copyright (C) 2017 SiFive 7 */ 8#ifndef _ASM_RISCV_HWCAP_H --- 66 unchanged lines hidden (view full) --- 75#define RISCV_ISA_EXT_ZFH 66 76#define RISCV_ISA_EXT_ZFHMIN 67 77#define RISCV_ISA_EXT_ZIHINTNTL 68 78#define RISCV_ISA_EXT_ZVFH 69 79#define RISCV_ISA_EXT_ZVFHMIN 70 80#define RISCV_ISA_EXT_ZFA 71 81#define RISCV_ISA_EXT_ZTSO 72 82#define RISCV_ISA_EXT_ZACAS 73 | 1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Copied from arch/arm64/include/asm/hwcap.h 4 * 5 * Copyright (C) 2012 ARM Ltd. 6 * Copyright (C) 2017 SiFive 7 */ 8#ifndef _ASM_RISCV_HWCAP_H --- 66 unchanged lines hidden (view full) --- 75#define RISCV_ISA_EXT_ZFH 66 76#define RISCV_ISA_EXT_ZFHMIN 67 77#define RISCV_ISA_EXT_ZIHINTNTL 68 78#define RISCV_ISA_EXT_ZVFH 69 79#define RISCV_ISA_EXT_ZVFHMIN 70 80#define RISCV_ISA_EXT_ZFA 71 81#define RISCV_ISA_EXT_ZTSO 72 82#define RISCV_ISA_EXT_ZACAS 73 |
| 83#define RISCV_ISA_EXT_XANDESPMU 74 84#define RISCV_ISA_EXT_ZVE32X 75 85#define RISCV_ISA_EXT_ZVE32F 76 86#define RISCV_ISA_EXT_ZVE64X 77 87#define RISCV_ISA_EXT_ZVE64F 78 88#define RISCV_ISA_EXT_ZVE64D 79 89#define RISCV_ISA_EXT_ZIMOP 80 90#define RISCV_ISA_EXT_ZCA 81 91#define RISCV_ISA_EXT_ZCB 82 92#define RISCV_ISA_EXT_ZCD 83 93#define RISCV_ISA_EXT_ZCF 84 94#define RISCV_ISA_EXT_ZCMOP 85 95#define RISCV_ISA_EXT_ZAWRS 86 | 83#define RISCV_ISA_EXT_ZVE32X 74 84#define RISCV_ISA_EXT_ZVE32F 75 85#define RISCV_ISA_EXT_ZVE64X 76 86#define RISCV_ISA_EXT_ZVE64F 77 87#define RISCV_ISA_EXT_ZVE64D 78 88#define RISCV_ISA_EXT_ZIMOP 79 89#define RISCV_ISA_EXT_ZCA 80 90#define RISCV_ISA_EXT_ZCB 81 91#define RISCV_ISA_EXT_ZCD 82 92#define RISCV_ISA_EXT_ZCF 83 93#define RISCV_ISA_EXT_ZCMOP 84 94#define RISCV_ISA_EXT_ZAWRS 85 |
| 96 97#define RISCV_ISA_EXT_XLINUXENVCFG 127 98 99#define RISCV_ISA_EXT_MAX 128 100#define RISCV_ISA_EXT_INVALID U32_MAX 101 102#ifdef CONFIG_RISCV_M_MODE 103#define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SMAIA 104#else 105#define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SSAIA 106#endif 107 108#endif /* _ASM_RISCV_HWCAP_H */ | 95 96#define RISCV_ISA_EXT_XLINUXENVCFG 127 97 98#define RISCV_ISA_EXT_MAX 128 99#define RISCV_ISA_EXT_INVALID U32_MAX 100 101#ifdef CONFIG_RISCV_M_MODE 102#define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SMAIA 103#else 104#define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SSAIA 105#endif 106 107#endif /* _ASM_RISCV_HWCAP_H */ |