jh7110.dtsi (ba817911855ce2ac3fd2a618aced1ce937353abe) jh7110.dtsi (466a885182857c437cf8527bb683a9064167fb61)
1// SPDX-License-Identifier: GPL-2.0 OR MIT
2/*
3 * Copyright (C) 2022 StarFive Technology Co., Ltd.
4 * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/starfive,jh7110-crg.h>

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671 clock-names = "ref";
672 resets = <&syscrg JH7110_SYSRST_I2C6_APB>;
673 interrupts = <51>;
674 #address-cells = <1>;
675 #size-cells = <0>;
676 status = "disabled";
677 };
678
1// SPDX-License-Identifier: GPL-2.0 OR MIT
2/*
3 * Copyright (C) 2022 StarFive Technology Co., Ltd.
4 * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/starfive,jh7110-crg.h>

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671 clock-names = "ref";
672 resets = <&syscrg JH7110_SYSRST_I2C6_APB>;
673 interrupts = <51>;
674 #address-cells = <1>;
675 #size-cells = <0>;
676 status = "disabled";
677 };
678
679 qspi: spi@13010000 {
680 compatible = "starfive,jh7110-qspi", "cdns,qspi-nor";
681 reg = <0x0 0x13010000 0x0 0x10000>,
682 <0x0 0x21000000 0x0 0x400000>;
683 interrupts = <25>;
684 clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>,
685 <&syscrg JH7110_SYSCLK_QSPI_AHB>,
686 <&syscrg JH7110_SYSCLK_QSPI_APB>;
687 clock-names = "ref", "ahb", "apb";
688 resets = <&syscrg JH7110_SYSRST_QSPI_APB>,
689 <&syscrg JH7110_SYSRST_QSPI_AHB>,
690 <&syscrg JH7110_SYSRST_QSPI_REF>;
691 reset-names = "qspi", "qspi-ocp", "rstc_ref";
692 cdns,fifo-depth = <256>;
693 cdns,fifo-width = <4>;
694 cdns,trigger-address = <0x0>;
695 status = "disabled";
696 };
697
698 spi3: spi@12070000 {
699 compatible = "arm,pl022", "arm,primecell";
700 reg = <0x0 0x12070000 0x0 0x10000>;
701 clocks = <&syscrg JH7110_SYSCLK_SPI3_APB>,
702 <&syscrg JH7110_SYSCLK_SPI3_APB>;
703 clock-names = "sspclk", "apb_pclk";
704 resets = <&syscrg JH7110_SYSRST_SPI3_APB>;
705 interrupts = <52>;

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762 <&syscrg JH7110_SYSCLK_TEMP_APB>;
763 clock-names = "sense", "bus";
764 resets = <&syscrg JH7110_SYSRST_TEMP_CORE>,
765 <&syscrg JH7110_SYSRST_TEMP_APB>;
766 reset-names = "sense", "bus";
767 #thermal-sensor-cells = <0>;
768 };
769
679 spi3: spi@12070000 {
680 compatible = "arm,pl022", "arm,primecell";
681 reg = <0x0 0x12070000 0x0 0x10000>;
682 clocks = <&syscrg JH7110_SYSCLK_SPI3_APB>,
683 <&syscrg JH7110_SYSCLK_SPI3_APB>;
684 clock-names = "sspclk", "apb_pclk";
685 resets = <&syscrg JH7110_SYSRST_SPI3_APB>;
686 interrupts = <52>;

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743 <&syscrg JH7110_SYSCLK_TEMP_APB>;
744 clock-names = "sense", "bus";
745 resets = <&syscrg JH7110_SYSRST_TEMP_CORE>,
746 <&syscrg JH7110_SYSRST_TEMP_APB>;
747 reset-names = "sense", "bus";
748 #thermal-sensor-cells = <0>;
749 };
750
751 qspi: spi@13010000 {
752 compatible = "starfive,jh7110-qspi", "cdns,qspi-nor";
753 reg = <0x0 0x13010000 0x0 0x10000>,
754 <0x0 0x21000000 0x0 0x400000>;
755 interrupts = <25>;
756 clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>,
757 <&syscrg JH7110_SYSCLK_QSPI_AHB>,
758 <&syscrg JH7110_SYSCLK_QSPI_APB>;
759 clock-names = "ref", "ahb", "apb";
760 resets = <&syscrg JH7110_SYSRST_QSPI_APB>,
761 <&syscrg JH7110_SYSRST_QSPI_AHB>,
762 <&syscrg JH7110_SYSRST_QSPI_REF>;
763 reset-names = "qspi", "qspi-ocp", "rstc_ref";
764 cdns,fifo-depth = <256>;
765 cdns,fifo-width = <4>;
766 cdns,trigger-address = <0x0>;
767 status = "disabled";
768 };
769
770 syscrg: clock-controller@13020000 {
771 compatible = "starfive,jh7110-syscrg";
772 reg = <0x0 0x13020000 0x0 0x10000>;
773 clocks = <&osc>, <&gmac1_rmii_refin>,
774 <&gmac1_rgmii_rxin>,
775 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
776 <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
777 <&tdm_ext>, <&mclk_ext>,

--- 272 unchanged lines hidden --- 		770 syscrg: clock-controller@13020000 {
771 compatible = "starfive,jh7110-syscrg";
772 reg = <0x0 0x13020000 0x0 0x10000>;
773 clocks = <&osc>, <&gmac1_rmii_refin>,
774 <&gmac1_rgmii_rxin>,
775 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
776 <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
777 <&tdm_ext>, <&mclk_ext>,

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