jh7110.dtsi (b127dbf9e1ebbfbcded4b339a5d37c066ef98c1c) jh7110.dtsi (e2c07765e179d0849326d4e1bd62ef8ba3d3cfd1)
1// SPDX-License-Identifier: GPL-2.0 OR MIT
2/*
3 * Copyright (C) 2022 StarFive Technology Co., Ltd.
4 * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/starfive,jh7110-crg.h>

--- 807 unchanged lines hidden (view full) ---

816 reg = <0x0 0x13070000 0x0 0x10000>;
817 clocks = <&syscrg JH7110_SYSCLK_WDT_APB>,
818 <&syscrg JH7110_SYSCLK_WDT_CORE>;
819 clock-names = "apb", "core";
820 resets = <&syscrg JH7110_SYSRST_WDT_APB>,
821 <&syscrg JH7110_SYSRST_WDT_CORE>;
822 };
823
1// SPDX-License-Identifier: GPL-2.0 OR MIT
2/*
3 * Copyright (C) 2022 StarFive Technology Co., Ltd.
4 * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/starfive,jh7110-crg.h>

--- 807 unchanged lines hidden (view full) ---

816 reg = <0x0 0x13070000 0x0 0x10000>;
817 clocks = <&syscrg JH7110_SYSCLK_WDT_APB>,
818 <&syscrg JH7110_SYSCLK_WDT_CORE>;
819 clock-names = "apb", "core";
820 resets = <&syscrg JH7110_SYSRST_WDT_APB>,
821 <&syscrg JH7110_SYSRST_WDT_CORE>;
822 };
823
824 crypto: crypto@16000000 {
825 compatible = "starfive,jh7110-crypto";
826 reg = <0x0 0x16000000 0x0 0x4000>;
827 clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>,
828 <&stgcrg JH7110_STGCLK_SEC_MISC_AHB>;
829 clock-names = "hclk", "ahb";
830 interrupts = <28>;
831 resets = <&stgcrg JH7110_STGRST_SEC_AHB>;
832 dmas = <&sdma 1 2>, <&sdma 0 2>;
833 dma-names = "tx", "rx";
834 };
835
836 sdma: dma-controller@16008000 {
837 compatible = "arm,pl080", "arm,primecell";
838 arm,primecell-periphid = <0x00041080>;
839 reg = <0x0 0x16008000 0x0 0x4000>;
840 interrupts = <29>;
841 clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>;
842 clock-names = "apb_pclk";
843 resets = <&stgcrg JH7110_STGRST_SEC_AHB>;
844 lli-bus-interface-ahb1;
845 mem-bus-interface-ahb1;
846 memcpy-burst-size = <256>;
847 memcpy-bus-width = <32>;
848 #dma-cells = <2>;
849 };
850
824 mmc0: mmc@16010000 {
825 compatible = "starfive,jh7110-mmc";
826 reg = <0x0 0x16010000 0x0 0x10000>;
827 clocks = <&syscrg JH7110_SYSCLK_SDIO0_AHB>,
828 <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
829 clock-names = "biu","ciu";
830 resets = <&syscrg JH7110_SYSRST_SDIO0_AHB>;
831 reset-names = "reset";

--- 181 unchanged lines hidden --- 		851 mmc0: mmc@16010000 {
852 compatible = "starfive,jh7110-mmc";
853 reg = <0x0 0x16010000 0x0 0x10000>;
854 clocks = <&syscrg JH7110_SYSCLK_SDIO0_AHB>,
855 <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
856 clock-names = "biu","ciu";
857 resets = <&syscrg JH7110_SYSRST_SDIO0_AHB>;
858 reset-names = "reset";

--- 181 unchanged lines hidden ---