jh7110.dtsi (50501936288d6a29d7ef78f25d00e33240fad45f) jh7110.dtsi (43f09605d11e62d70a2979e85167bbc9d4b2617e)
1// SPDX-License-Identifier: GPL-2.0 OR MIT
2/*
3 * Copyright (C) 2022 StarFive Technology Co., Ltd.
4 * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/starfive,jh7110-crg.h>

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48 i-cache-sets = <64>;
49 i-cache-size = <32768>;
50 i-tlb-sets = <1>;
51 i-tlb-size = <40>;
52 mmu-type = "riscv,sv39";
53 next-level-cache = <&ccache>;
54 riscv,isa = "rv64imafdc_zba_zbb";
55 tlb-split;
1// SPDX-License-Identifier: GPL-2.0 OR MIT
2/*
3 * Copyright (C) 2022 StarFive Technology Co., Ltd.
4 * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/starfive,jh7110-crg.h>

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48 i-cache-sets = <64>;
49 i-cache-size = <32768>;
50 i-tlb-sets = <1>;
51 i-tlb-size = <40>;
52 mmu-type = "riscv,sv39";
53 next-level-cache = <&ccache>;
54 riscv,isa = "rv64imafdc_zba_zbb";
55 tlb-split;
56 operating-points-v2 = <&cpu_opp>;
57 clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
58 clock-names = "cpu";
56
57 cpu1_intc: interrupt-controller {
58 compatible = "riscv,cpu-intc";
59 interrupt-controller;
60 #interrupt-cells = <1>;
61 };
62 };
63

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74 i-cache-sets = <64>;
75 i-cache-size = <32768>;
76 i-tlb-sets = <1>;
77 i-tlb-size = <40>;
78 mmu-type = "riscv,sv39";
79 next-level-cache = <&ccache>;
80 riscv,isa = "rv64imafdc_zba_zbb";
81 tlb-split;
59
60 cpu1_intc: interrupt-controller {
61 compatible = "riscv,cpu-intc";
62 interrupt-controller;
63 #interrupt-cells = <1>;
64 };
65 };
66

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77 i-cache-sets = <64>;
78 i-cache-size = <32768>;
79 i-tlb-sets = <1>;
80 i-tlb-size = <40>;
81 mmu-type = "riscv,sv39";
82 next-level-cache = <&ccache>;
83 riscv,isa = "rv64imafdc_zba_zbb";
84 tlb-split;
85 operating-points-v2 = <&cpu_opp>;
86 clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
87 clock-names = "cpu";
82
83 cpu2_intc: interrupt-controller {
84 compatible = "riscv,cpu-intc";
85 interrupt-controller;
86 #interrupt-cells = <1>;
87 };
88 };
89

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100 i-cache-sets = <64>;
101 i-cache-size = <32768>;
102 i-tlb-sets = <1>;
103 i-tlb-size = <40>;
104 mmu-type = "riscv,sv39";
105 next-level-cache = <&ccache>;
106 riscv,isa = "rv64imafdc_zba_zbb";
107 tlb-split;
88
89 cpu2_intc: interrupt-controller {
90 compatible = "riscv,cpu-intc";
91 interrupt-controller;
92 #interrupt-cells = <1>;
93 };
94 };
95

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106 i-cache-sets = <64>;
107 i-cache-size = <32768>;
108 i-tlb-sets = <1>;
109 i-tlb-size = <40>;
110 mmu-type = "riscv,sv39";
111 next-level-cache = <&ccache>;
112 riscv,isa = "rv64imafdc_zba_zbb";
113 tlb-split;
114 operating-points-v2 = <&cpu_opp>;
115 clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
116 clock-names = "cpu";
108
109 cpu3_intc: interrupt-controller {
110 compatible = "riscv,cpu-intc";
111 interrupt-controller;
112 #interrupt-cells = <1>;
113 };
114 };
115

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126 i-cache-sets = <64>;
127 i-cache-size = <32768>;
128 i-tlb-sets = <1>;
129 i-tlb-size = <40>;
130 mmu-type = "riscv,sv39";
131 next-level-cache = <&ccache>;
132 riscv,isa = "rv64imafdc_zba_zbb";
133 tlb-split;
117
118 cpu3_intc: interrupt-controller {
119 compatible = "riscv,cpu-intc";
120 interrupt-controller;
121 #interrupt-cells = <1>;
122 };
123 };
124

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135 i-cache-sets = <64>;
136 i-cache-size = <32768>;
137 i-tlb-sets = <1>;
138 i-tlb-size = <40>;
139 mmu-type = "riscv,sv39";
140 next-level-cache = <&ccache>;
141 riscv,isa = "rv64imafdc_zba_zbb";
142 tlb-split;
143 operating-points-v2 = <&cpu_opp>;
144 clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
145 clock-names = "cpu";
134
135 cpu4_intc: interrupt-controller {
136 compatible = "riscv,cpu-intc";
137 interrupt-controller;
138 #interrupt-cells = <1>;
139 };
140 };
141

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159
160 core4 {
161 cpu = <&U74_4>;
162 };
163 };
164 };
165 };
166
146
147 cpu4_intc: interrupt-controller {
148 compatible = "riscv,cpu-intc";
149 interrupt-controller;
150 #interrupt-cells = <1>;
151 };
152 };
153

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171
172 core4 {
173 cpu = <&U74_4>;
174 };
175 };
176 };
177 };
178
179 cpu_opp: opp-table-0 {
180 compatible = "operating-points-v2";
181 opp-shared;
182 opp-375000000 {
183 opp-hz = /bits/ 64 <375000000>;
184 opp-microvolt = <800000>;
185 };
186 opp-500000000 {
187 opp-hz = /bits/ 64 <500000000>;
188 opp-microvolt = <800000>;
189 };
190 opp-750000000 {
191 opp-hz = /bits/ 64 <750000000>;
192 opp-microvolt = <800000>;
193 };
194 opp-1500000000 {
195 opp-hz = /bits/ 64 <1500000000>;
196 opp-microvolt = <1040000>;
197 };
198 };
199
200 dvp_clk: dvp-clock {
201 compatible = "fixed-clock";
202 clock-output-names = "dvp_clk";
203 #clock-cells = <0>;
204 };
205
167 gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock {
168 compatible = "fixed-clock";
169 clock-output-names = "gmac0_rgmii_rxin";
170 #clock-cells = <0>;
171 };
172
173 gmac0_rmii_refin: gmac0-rmii-refin-clock {
174 compatible = "fixed-clock";

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183 };
184
185 gmac1_rmii_refin: gmac1-rmii-refin-clock {
186 compatible = "fixed-clock";
187 clock-output-names = "gmac1_rmii_refin";
188 #clock-cells = <0>;
189 };
190
206 gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock {
207 compatible = "fixed-clock";
208 clock-output-names = "gmac0_rgmii_rxin";
209 #clock-cells = <0>;
210 };
211
212 gmac0_rmii_refin: gmac0-rmii-refin-clock {
213 compatible = "fixed-clock";

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222 };
223
224 gmac1_rmii_refin: gmac1-rmii-refin-clock {
225 compatible = "fixed-clock";
226 clock-output-names = "gmac1_rmii_refin";
227 #clock-cells = <0>;
228 };
229
230 hdmitx0_pixelclk: hdmitx0-pixel-clock {
231 compatible = "fixed-clock";
232 clock-output-names = "hdmitx0_pixelclk";
233 #clock-cells = <0>;
234 };
235
191 i2srx_bclk_ext: i2srx-bclk-ext-clock {
192 compatible = "fixed-clock";
193 clock-output-names = "i2srx_bclk_ext";
194 #clock-cells = <0>;
195 };
196
197 i2srx_lrck_ext: i2srx-lrck-ext-clock {
198 compatible = "fixed-clock";

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464 resets = <&syscrg JH7110_SYSRST_IOMUX_APB>;
465 interrupts = <86>;
466 interrupt-controller;
467 #interrupt-cells = <2>;
468 gpio-controller;
469 #gpio-cells = <2>;
470 };
471
236 i2srx_bclk_ext: i2srx-bclk-ext-clock {
237 compatible = "fixed-clock";
238 clock-output-names = "i2srx_bclk_ext";
239 #clock-cells = <0>;
240 };
241
242 i2srx_lrck_ext: i2srx-lrck-ext-clock {
243 compatible = "fixed-clock";

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509 resets = <&syscrg JH7110_SYSRST_IOMUX_APB>;
510 interrupts = <86>;
511 interrupt-controller;
512 #interrupt-cells = <2>;
513 gpio-controller;
514 #gpio-cells = <2>;
515 };
516
517 watchdog@13070000 {
518 compatible = "starfive,jh7110-wdt";
519 reg = <0x0 0x13070000 0x0 0x10000>;
520 clocks = <&syscrg JH7110_SYSCLK_WDT_APB>,
521 <&syscrg JH7110_SYSCLK_WDT_CORE>;
522 clock-names = "apb", "core";
523 resets = <&syscrg JH7110_SYSRST_WDT_APB>,
524 <&syscrg JH7110_SYSRST_WDT_CORE>;
525 };
526
472 aoncrg: clock-controller@17000000 {
473 compatible = "starfive,jh7110-aoncrg";
474 reg = <0x0 0x17000000 0x0 0x10000>;
475 clocks = <&osc>, <&gmac0_rmii_refin>,
476 <&gmac0_rgmii_rxin>,
477 <&syscrg JH7110_SYSCLK_STG_AXIAHB>,
478 <&syscrg JH7110_SYSCLK_APB_BUS>,
479 <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>,

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491 reg = <0x0 0x17020000 0x0 0x10000>;
492 resets = <&aoncrg JH7110_AONRST_IOMUX>;
493 interrupts = <85>;
494 interrupt-controller;
495 #interrupt-cells = <2>;
496 gpio-controller;
497 #gpio-cells = <2>;
498 };
527 aoncrg: clock-controller@17000000 {
528 compatible = "starfive,jh7110-aoncrg";
529 reg = <0x0 0x17000000 0x0 0x10000>;
530 clocks = <&osc>, <&gmac0_rmii_refin>,
531 <&gmac0_rgmii_rxin>,
532 <&syscrg JH7110_SYSCLK_STG_AXIAHB>,
533 <&syscrg JH7110_SYSCLK_APB_BUS>,
534 <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>,

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546 reg = <0x0 0x17020000 0x0 0x10000>;
547 resets = <&aoncrg JH7110_AONRST_IOMUX>;
548 interrupts = <85>;
549 interrupt-controller;
550 #interrupt-cells = <2>;
551 gpio-controller;
552 #gpio-cells = <2>;
553 };
554
555 pwrc: power-controller@17030000 {
556 compatible = "starfive,jh7110-pmu";
557 reg = <0x0 0x17030000 0x0 0x10000>;
558 interrupts = <111>;
559 #power-domain-cells = <1>;
560 };
499 };
500};
561 };
562};