jh7110.dtsi (2612e3bbc0386368a850140a6c9b990cd496a5ec) jh7110.dtsi (b127dbf9e1ebbfbcded4b339a5d37c066ef98c1c)
1// SPDX-License-Identifier: GPL-2.0 OR MIT
2/*
3 * Copyright (C) 2022 StarFive Technology Co., Ltd.
4 * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/starfive,jh7110-crg.h>
1// SPDX-License-Identifier: GPL-2.0 OR MIT
2/*
3 * Copyright (C) 2022 StarFive Technology Co., Ltd.
4 * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
5 */
6
7/dts-v1/;
8#include <dt-bindings/clock/starfive,jh7110-crg.h>
9#include <dt-bindings/power/starfive,jh7110-pmu.h>
9#include <dt-bindings/reset/starfive,jh7110-crg.h>
10#include <dt-bindings/reset/starfive,jh7110-crg.h>
11#include <dt-bindings/thermal/thermal.h>
10
11/ {
12 compatible = "starfive,jh7110";
13 #address-cells = <2>;
14 #size-cells = <2>;
15
16 cpus {
17 #address-cells = <1>;

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51 i-tlb-size = <40>;
52 mmu-type = "riscv,sv39";
53 next-level-cache = <&ccache>;
54 riscv,isa = "rv64imafdc_zba_zbb";
55 tlb-split;
56 operating-points-v2 = <&cpu_opp>;
57 clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
58 clock-names = "cpu";
12
13/ {
14 compatible = "starfive,jh7110";
15 #address-cells = <2>;
16 #size-cells = <2>;
17
18 cpus {
19 #address-cells = <1>;

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53 i-tlb-size = <40>;
54 mmu-type = "riscv,sv39";
55 next-level-cache = <&ccache>;
56 riscv,isa = "rv64imafdc_zba_zbb";
57 tlb-split;
58 operating-points-v2 = <&cpu_opp>;
59 clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
60 clock-names = "cpu";
61 #cooling-cells = <2>;
59
60 cpu1_intc: interrupt-controller {
61 compatible = "riscv,cpu-intc";
62 interrupt-controller;
63 #interrupt-cells = <1>;
64 };
65 };
66

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80 i-tlb-size = <40>;
81 mmu-type = "riscv,sv39";
82 next-level-cache = <&ccache>;
83 riscv,isa = "rv64imafdc_zba_zbb";
84 tlb-split;
85 operating-points-v2 = <&cpu_opp>;
86 clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
87 clock-names = "cpu";
62
63 cpu1_intc: interrupt-controller {
64 compatible = "riscv,cpu-intc";
65 interrupt-controller;
66 #interrupt-cells = <1>;
67 };
68 };
69

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83 i-tlb-size = <40>;
84 mmu-type = "riscv,sv39";
85 next-level-cache = <&ccache>;
86 riscv,isa = "rv64imafdc_zba_zbb";
87 tlb-split;
88 operating-points-v2 = <&cpu_opp>;
89 clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
90 clock-names = "cpu";
91 #cooling-cells = <2>;
88
89 cpu2_intc: interrupt-controller {
90 compatible = "riscv,cpu-intc";
91 interrupt-controller;
92 #interrupt-cells = <1>;
93 };
94 };
95

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109 i-tlb-size = <40>;
110 mmu-type = "riscv,sv39";
111 next-level-cache = <&ccache>;
112 riscv,isa = "rv64imafdc_zba_zbb";
113 tlb-split;
114 operating-points-v2 = <&cpu_opp>;
115 clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
116 clock-names = "cpu";
92
93 cpu2_intc: interrupt-controller {
94 compatible = "riscv,cpu-intc";
95 interrupt-controller;
96 #interrupt-cells = <1>;
97 };
98 };
99

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113 i-tlb-size = <40>;
114 mmu-type = "riscv,sv39";
115 next-level-cache = <&ccache>;
116 riscv,isa = "rv64imafdc_zba_zbb";
117 tlb-split;
118 operating-points-v2 = <&cpu_opp>;
119 clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
120 clock-names = "cpu";
121 #cooling-cells = <2>;
117
118 cpu3_intc: interrupt-controller {
119 compatible = "riscv,cpu-intc";
120 interrupt-controller;
121 #interrupt-cells = <1>;
122 };
123 };
124

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138 i-tlb-size = <40>;
139 mmu-type = "riscv,sv39";
140 next-level-cache = <&ccache>;
141 riscv,isa = "rv64imafdc_zba_zbb";
142 tlb-split;
143 operating-points-v2 = <&cpu_opp>;
144 clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
145 clock-names = "cpu";
122
123 cpu3_intc: interrupt-controller {
124 compatible = "riscv,cpu-intc";
125 interrupt-controller;
126 #interrupt-cells = <1>;
127 };
128 };
129

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143 i-tlb-size = <40>;
144 mmu-type = "riscv,sv39";
145 next-level-cache = <&ccache>;
146 riscv,isa = "rv64imafdc_zba_zbb";
147 tlb-split;
148 operating-points-v2 = <&cpu_opp>;
149 clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
150 clock-names = "cpu";
151 #cooling-cells = <2>;
146
147 cpu4_intc: interrupt-controller {
148 compatible = "riscv,cpu-intc";
149 interrupt-controller;
150 #interrupt-cells = <1>;
151 };
152 };
153

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192 opp-microvolt = <800000>;
193 };
194 opp-1500000000 {
195 opp-hz = /bits/ 64 <1500000000>;
196 opp-microvolt = <1040000>;
197 };
198 };
199
152
153 cpu4_intc: interrupt-controller {
154 compatible = "riscv,cpu-intc";
155 interrupt-controller;
156 #interrupt-cells = <1>;
157 };
158 };
159

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198 opp-microvolt = <800000>;
199 };
200 opp-1500000000 {
201 opp-hz = /bits/ 64 <1500000000>;
202 opp-microvolt = <1040000>;
203 };
204 };
205
206 thermal-zones {
207 cpu-thermal {
208 polling-delay-passive = <250>;
209 polling-delay = <15000>;
210
211 thermal-sensors = <&sfctemp>;
212
213 cooling-maps {
214 map0 {
215 trip = <&cpu_alert0>;
216 cooling-device =
217 <&U74_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
218 <&U74_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
219 <&U74_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
220 <&U74_4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
221 };
222 };
223
224 trips {
225 cpu_alert0: cpu_alert0 {
226 /* milliCelsius */
227 temperature = <85000>;
228 hysteresis = <2000>;
229 type = "passive";
230 };
231
232 cpu_crit {
233 /* milliCelsius */
234 temperature = <100000>;
235 hysteresis = <2000>;
236 type = "critical";
237 };
238 };
239 };
240 };
241
242 dvp_clk: dvp-clock {
243 compatible = "fixed-clock";
244 clock-output-names = "dvp_clk";
245 #clock-cells = <0>;
246 };
200 gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock {
201 compatible = "fixed-clock";
202 clock-output-names = "gmac0_rgmii_rxin";
203 #clock-cells = <0>;
204 };
205
206 gmac0_rmii_refin: gmac0-rmii-refin-clock {
207 compatible = "fixed-clock";

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216 };
217
218 gmac1_rmii_refin: gmac1-rmii-refin-clock {
219 compatible = "fixed-clock";
220 clock-output-names = "gmac1_rmii_refin";
221 #clock-cells = <0>;
222 };
223
247 gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock {
248 compatible = "fixed-clock";
249 clock-output-names = "gmac0_rgmii_rxin";
250 #clock-cells = <0>;
251 };
252
253 gmac0_rmii_refin: gmac0-rmii-refin-clock {
254 compatible = "fixed-clock";

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263 };
264
265 gmac1_rmii_refin: gmac1-rmii-refin-clock {
266 compatible = "fixed-clock";
267 clock-output-names = "gmac1_rmii_refin";
268 #clock-cells = <0>;
269 };
270
271 hdmitx0_pixelclk: hdmitx0-pixel-clock {
272 compatible = "fixed-clock";
273 clock-output-names = "hdmitx0_pixelclk";
274 #clock-cells = <0>;
275 };
276
224 i2srx_bclk_ext: i2srx-bclk-ext-clock {
225 compatible = "fixed-clock";
226 clock-output-names = "i2srx_bclk_ext";
227 #clock-cells = <0>;
228 };
229
230 i2srx_lrck_ext: i2srx-lrck-ext-clock {
231 compatible = "fixed-clock";

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258 };
259
260 rtc_osc: rtc-oscillator {
261 compatible = "fixed-clock";
262 clock-output-names = "rtc_osc";
263 #clock-cells = <0>;
264 };
265
277 i2srx_bclk_ext: i2srx-bclk-ext-clock {
278 compatible = "fixed-clock";
279 clock-output-names = "i2srx_bclk_ext";
280 #clock-cells = <0>;
281 };
282
283 i2srx_lrck_ext: i2srx-lrck-ext-clock {
284 compatible = "fixed-clock";

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311 };
312
313 rtc_osc: rtc-oscillator {
314 compatible = "fixed-clock";
315 clock-output-names = "rtc_osc";
316 #clock-cells = <0>;
317 };
318
319 stmmac_axi_setup: stmmac-axi-config {
320 snps,lpi_en;
321 snps,wr_osr_lmt = <4>;
322 snps,rd_osr_lmt = <4>;
323 snps,blen = <256 128 64 32 0 0 0>;
324 };
325
266 tdm_ext: tdm-ext-clock {
267 compatible = "fixed-clock";
268 clock-output-names = "tdm_ext";
269 #clock-cells = <0>;
270 };
271
272 soc {
273 compatible = "simple-bus";

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381 clock-names = "ref";
382 resets = <&syscrg JH7110_SYSRST_I2C2_APB>;
383 interrupts = <37>;
384 #address-cells = <1>;
385 #size-cells = <0>;
386 status = "disabled";
387 };
388
326 tdm_ext: tdm-ext-clock {
327 compatible = "fixed-clock";
328 clock-output-names = "tdm_ext";
329 #clock-cells = <0>;
330 };
331
332 soc {
333 compatible = "simple-bus";

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441 clock-names = "ref";
442 resets = <&syscrg JH7110_SYSRST_I2C2_APB>;
443 interrupts = <37>;
444 #address-cells = <1>;
445 #size-cells = <0>;
446 status = "disabled";
447 };
448
449 spi0: spi@10060000 {
450 compatible = "arm,pl022", "arm,primecell";
451 reg = <0x0 0x10060000 0x0 0x10000>;
452 clocks = <&syscrg JH7110_SYSCLK_SPI0_APB>,
453 <&syscrg JH7110_SYSCLK_SPI0_APB>;
454 clock-names = "sspclk", "apb_pclk";
455 resets = <&syscrg JH7110_SYSRST_SPI0_APB>;
456 interrupts = <38>;
457 arm,primecell-periphid = <0x00041022>;
458 num-cs = <1>;
459 #address-cells = <1>;
460 #size-cells = <0>;
461 status = "disabled";
462 };
463
464 spi1: spi@10070000 {
465 compatible = "arm,pl022", "arm,primecell";
466 reg = <0x0 0x10070000 0x0 0x10000>;
467 clocks = <&syscrg JH7110_SYSCLK_SPI1_APB>,
468 <&syscrg JH7110_SYSCLK_SPI1_APB>;
469 clock-names = "sspclk", "apb_pclk";
470 resets = <&syscrg JH7110_SYSRST_SPI1_APB>;
471 interrupts = <39>;
472 arm,primecell-periphid = <0x00041022>;
473 num-cs = <1>;
474 #address-cells = <1>;
475 #size-cells = <0>;
476 status = "disabled";
477 };
478
479 spi2: spi@10080000 {
480 compatible = "arm,pl022", "arm,primecell";
481 reg = <0x0 0x10080000 0x0 0x10000>;
482 clocks = <&syscrg JH7110_SYSCLK_SPI2_APB>,
483 <&syscrg JH7110_SYSCLK_SPI2_APB>;
484 clock-names = "sspclk", "apb_pclk";
485 resets = <&syscrg JH7110_SYSRST_SPI2_APB>;
486 interrupts = <40>;
487 arm,primecell-periphid = <0x00041022>;
488 num-cs = <1>;
489 #address-cells = <1>;
490 #size-cells = <0>;
491 status = "disabled";
492 };
493
494 tdm: tdm@10090000 {
495 compatible = "starfive,jh7110-tdm";
496 reg = <0x0 0x10090000 0x0 0x1000>;
497 clocks = <&syscrg JH7110_SYSCLK_TDM_AHB>,
498 <&syscrg JH7110_SYSCLK_TDM_APB>,
499 <&syscrg JH7110_SYSCLK_TDM_INTERNAL>,
500 <&syscrg JH7110_SYSCLK_TDM_TDM>,
501 <&syscrg JH7110_SYSCLK_MCLK_INNER>,
502 <&tdm_ext>;
503 clock-names = "tdm_ahb", "tdm_apb",
504 "tdm_internal", "tdm",
505 "mclk_inner", "tdm_ext";
506 resets = <&syscrg JH7110_SYSRST_TDM_AHB>,
507 <&syscrg JH7110_SYSRST_TDM_APB>,
508 <&syscrg JH7110_SYSRST_TDM_CORE>;
509 dmas = <&dma 20>, <&dma 21>;
510 dma-names = "rx","tx";
511 #sound-dai-cells = <0>;
512 status = "disabled";
513 };
514
515 usb0: usb@10100000 {
516 compatible = "starfive,jh7110-usb";
517 ranges = <0x0 0x0 0x10100000 0x100000>;
518 #address-cells = <1>;
519 #size-cells = <1>;
520 starfive,stg-syscon = <&stg_syscon 0x4>;
521 clocks = <&stgcrg JH7110_STGCLK_USB0_LPM>,
522 <&stgcrg JH7110_STGCLK_USB0_STB>,
523 <&stgcrg JH7110_STGCLK_USB0_APB>,
524 <&stgcrg JH7110_STGCLK_USB0_AXI>,
525 <&stgcrg JH7110_STGCLK_USB0_UTMI_APB>;
526 clock-names = "lpm", "stb", "apb", "axi", "utmi_apb";
527 resets = <&stgcrg JH7110_STGRST_USB0_PWRUP>,
528 <&stgcrg JH7110_STGRST_USB0_APB>,
529 <&stgcrg JH7110_STGRST_USB0_AXI>,
530 <&stgcrg JH7110_STGRST_USB0_UTMI_APB>;
531 reset-names = "pwrup", "apb", "axi", "utmi_apb";
532 status = "disabled";
533
534 usb_cdns3: usb@0 {
535 compatible = "cdns,usb3";
536 reg = <0x0 0x10000>,
537 <0x10000 0x10000>,
538 <0x20000 0x10000>;
539 reg-names = "otg", "xhci", "dev";
540 interrupts = <100>, <108>, <110>;
541 interrupt-names = "host", "peripheral", "otg";
542 phys = <&usbphy0>;
543 phy-names = "cdns3,usb2-phy";
544 };
545 };
546
547 usbphy0: phy@10200000 {
548 compatible = "starfive,jh7110-usb-phy";
549 reg = <0x0 0x10200000 0x0 0x10000>;
550 clocks = <&syscrg JH7110_SYSCLK_USB_125M>,
551 <&stgcrg JH7110_STGCLK_USB0_APP_125>;
552 clock-names = "125m", "app_125m";
553 #phy-cells = <0>;
554 };
555
556 pciephy0: phy@10210000 {
557 compatible = "starfive,jh7110-pcie-phy";
558 reg = <0x0 0x10210000 0x0 0x10000>;
559 #phy-cells = <0>;
560 };
561
562 pciephy1: phy@10220000 {
563 compatible = "starfive,jh7110-pcie-phy";
564 reg = <0x0 0x10220000 0x0 0x10000>;
565 #phy-cells = <0>;
566 };
567
568 stgcrg: clock-controller@10230000 {
569 compatible = "starfive,jh7110-stgcrg";
570 reg = <0x0 0x10230000 0x0 0x10000>;
571 clocks = <&osc>,
572 <&syscrg JH7110_SYSCLK_HIFI4_CORE>,
573 <&syscrg JH7110_SYSCLK_STG_AXIAHB>,
574 <&syscrg JH7110_SYSCLK_USB_125M>,
575 <&syscrg JH7110_SYSCLK_CPU_BUS>,
576 <&syscrg JH7110_SYSCLK_HIFI4_AXI>,
577 <&syscrg JH7110_SYSCLK_NOCSTG_BUS>,
578 <&syscrg JH7110_SYSCLK_APB_BUS>;
579 clock-names = "osc", "hifi4_core",
580 "stg_axiahb", "usb_125m",
581 "cpu_bus", "hifi4_axi",
582 "nocstg_bus", "apb_bus";
583 #clock-cells = <1>;
584 #reset-cells = <1>;
585 };
586
587 stg_syscon: syscon@10240000 {
588 compatible = "starfive,jh7110-stg-syscon", "syscon";
589 reg = <0x0 0x10240000 0x0 0x1000>;
590 };
591
389 uart3: serial@12000000 {
390 compatible = "snps,dw-apb-uart";
391 reg = <0x0 0x12000000 0x0 0x10000>;
392 clocks = <&syscrg JH7110_SYSCLK_UART3_CORE>,
393 <&syscrg JH7110_SYSCLK_UART3_APB>;
394 clock-names = "baudclk", "apb_pclk";
395 resets = <&syscrg JH7110_SYSRST_UART3_APB>;
396 interrupts = <45>;

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468 clock-names = "ref";
469 resets = <&syscrg JH7110_SYSRST_I2C6_APB>;
470 interrupts = <51>;
471 #address-cells = <1>;
472 #size-cells = <0>;
473 status = "disabled";
474 };
475
592 uart3: serial@12000000 {
593 compatible = "snps,dw-apb-uart";
594 reg = <0x0 0x12000000 0x0 0x10000>;
595 clocks = <&syscrg JH7110_SYSCLK_UART3_CORE>,
596 <&syscrg JH7110_SYSCLK_UART3_APB>;
597 clock-names = "baudclk", "apb_pclk";
598 resets = <&syscrg JH7110_SYSRST_UART3_APB>;
599 interrupts = <45>;

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671 clock-names = "ref";
672 resets = <&syscrg JH7110_SYSRST_I2C6_APB>;
673 interrupts = <51>;
674 #address-cells = <1>;
675 #size-cells = <0>;
676 status = "disabled";
677 };
678
679 qspi: spi@13010000 {
680 compatible = "starfive,jh7110-qspi", "cdns,qspi-nor";
681 reg = <0x0 0x13010000 0x0 0x10000>,
682 <0x0 0x21000000 0x0 0x400000>;
683 interrupts = <25>;
684 clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>,
685 <&syscrg JH7110_SYSCLK_QSPI_AHB>,
686 <&syscrg JH7110_SYSCLK_QSPI_APB>;
687 clock-names = "ref", "ahb", "apb";
688 resets = <&syscrg JH7110_SYSRST_QSPI_APB>,
689 <&syscrg JH7110_SYSRST_QSPI_AHB>,
690 <&syscrg JH7110_SYSRST_QSPI_REF>;
691 reset-names = "qspi", "qspi-ocp", "rstc_ref";
692 cdns,fifo-depth = <256>;
693 cdns,fifo-width = <4>;
694 cdns,trigger-address = <0x0>;
695 status = "disabled";
696 };
697
698 spi3: spi@12070000 {
699 compatible = "arm,pl022", "arm,primecell";
700 reg = <0x0 0x12070000 0x0 0x10000>;
701 clocks = <&syscrg JH7110_SYSCLK_SPI3_APB>,
702 <&syscrg JH7110_SYSCLK_SPI3_APB>;
703 clock-names = "sspclk", "apb_pclk";
704 resets = <&syscrg JH7110_SYSRST_SPI3_APB>;
705 interrupts = <52>;
706 arm,primecell-periphid = <0x00041022>;
707 num-cs = <1>;
708 #address-cells = <1>;
709 #size-cells = <0>;
710 status = "disabled";
711 };
712
713 spi4: spi@12080000 {
714 compatible = "arm,pl022", "arm,primecell";
715 reg = <0x0 0x12080000 0x0 0x10000>;
716 clocks = <&syscrg JH7110_SYSCLK_SPI4_APB>,
717 <&syscrg JH7110_SYSCLK_SPI4_APB>;
718 clock-names = "sspclk", "apb_pclk";
719 resets = <&syscrg JH7110_SYSRST_SPI4_APB>;
720 interrupts = <53>;
721 arm,primecell-periphid = <0x00041022>;
722 num-cs = <1>;
723 #address-cells = <1>;
724 #size-cells = <0>;
725 status = "disabled";
726 };
727
728 spi5: spi@12090000 {
729 compatible = "arm,pl022", "arm,primecell";
730 reg = <0x0 0x12090000 0x0 0x10000>;
731 clocks = <&syscrg JH7110_SYSCLK_SPI5_APB>,
732 <&syscrg JH7110_SYSCLK_SPI5_APB>;
733 clock-names = "sspclk", "apb_pclk";
734 resets = <&syscrg JH7110_SYSRST_SPI5_APB>;
735 interrupts = <54>;
736 arm,primecell-periphid = <0x00041022>;
737 num-cs = <1>;
738 #address-cells = <1>;
739 #size-cells = <0>;
740 status = "disabled";
741 };
742
743 spi6: spi@120a0000 {
744 compatible = "arm,pl022", "arm,primecell";
745 reg = <0x0 0x120A0000 0x0 0x10000>;
746 clocks = <&syscrg JH7110_SYSCLK_SPI6_APB>,
747 <&syscrg JH7110_SYSCLK_SPI6_APB>;
748 clock-names = "sspclk", "apb_pclk";
749 resets = <&syscrg JH7110_SYSRST_SPI6_APB>;
750 interrupts = <55>;
751 arm,primecell-periphid = <0x00041022>;
752 num-cs = <1>;
753 #address-cells = <1>;
754 #size-cells = <0>;
755 status = "disabled";
756 };
757
758 sfctemp: temperature-sensor@120e0000 {
759 compatible = "starfive,jh7110-temp";
760 reg = <0x0 0x120e0000 0x0 0x10000>;
761 clocks = <&syscrg JH7110_SYSCLK_TEMP_CORE>,
762 <&syscrg JH7110_SYSCLK_TEMP_APB>;
763 clock-names = "sense", "bus";
764 resets = <&syscrg JH7110_SYSRST_TEMP_CORE>,
765 <&syscrg JH7110_SYSRST_TEMP_APB>;
766 reset-names = "sense", "bus";
767 #thermal-sensor-cells = <0>;
768 };
769
476 syscrg: clock-controller@13020000 {
477 compatible = "starfive,jh7110-syscrg";
478 reg = <0x0 0x13020000 0x0 0x10000>;
479 clocks = <&osc>, <&gmac1_rmii_refin>,
480 <&gmac1_rgmii_rxin>,
481 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
482 <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
770 syscrg: clock-controller@13020000 {
771 compatible = "starfive,jh7110-syscrg";
772 reg = <0x0 0x13020000 0x0 0x10000>;
773 clocks = <&osc>, <&gmac1_rmii_refin>,
774 <&gmac1_rgmii_rxin>,
775 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
776 <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
483 <&tdm_ext>, <&mclk_ext>;
777 <&tdm_ext>, <&mclk_ext>,
778 <&pllclk JH7110_PLLCLK_PLL0_OUT>,
779 <&pllclk JH7110_PLLCLK_PLL1_OUT>,
780 <&pllclk JH7110_PLLCLK_PLL2_OUT>;
484 clock-names = "osc", "gmac1_rmii_refin",
485 "gmac1_rgmii_rxin",
486 "i2stx_bclk_ext", "i2stx_lrck_ext",
487 "i2srx_bclk_ext", "i2srx_lrck_ext",
781 clock-names = "osc", "gmac1_rmii_refin",
782 "gmac1_rgmii_rxin",
783 "i2stx_bclk_ext", "i2stx_lrck_ext",
784 "i2srx_bclk_ext", "i2srx_lrck_ext",
488 "tdm_ext", "mclk_ext";
785 "tdm_ext", "mclk_ext",
786 "pll0_out", "pll1_out", "pll2_out";
489 #clock-cells = <1>;
490 #reset-cells = <1>;
491 };
492
787 #clock-cells = <1>;
788 #reset-cells = <1>;
789 };
790
791 sys_syscon: syscon@13030000 {
792 compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd";
793 reg = <0x0 0x13030000 0x0 0x1000>;
794
795 pllclk: clock-controller {
796 compatible = "starfive,jh7110-pll";
797 clocks = <&osc>;
798 #clock-cells = <1>;
799 };
800 };
801
493 sysgpio: pinctrl@13040000 {
494 compatible = "starfive,jh7110-sys-pinctrl";
495 reg = <0x0 0x13040000 0x0 0x10000>;
496 clocks = <&syscrg JH7110_SYSCLK_IOMUX_APB>;
497 resets = <&syscrg JH7110_SYSRST_IOMUX_APB>;
498 interrupts = <86>;
499 interrupt-controller;
500 #interrupt-cells = <2>;

--- 6 unchanged lines hidden (view full) ---

507 reg = <0x0 0x13070000 0x0 0x10000>;
508 clocks = <&syscrg JH7110_SYSCLK_WDT_APB>,
509 <&syscrg JH7110_SYSCLK_WDT_CORE>;
510 clock-names = "apb", "core";
511 resets = <&syscrg JH7110_SYSRST_WDT_APB>,
512 <&syscrg JH7110_SYSRST_WDT_CORE>;
513 };
514
802 sysgpio: pinctrl@13040000 {
803 compatible = "starfive,jh7110-sys-pinctrl";
804 reg = <0x0 0x13040000 0x0 0x10000>;
805 clocks = <&syscrg JH7110_SYSCLK_IOMUX_APB>;
806 resets = <&syscrg JH7110_SYSRST_IOMUX_APB>;
807 interrupts = <86>;
808 interrupt-controller;
809 #interrupt-cells = <2>;

--- 6 unchanged lines hidden (view full) ---

816 reg = <0x0 0x13070000 0x0 0x10000>;
817 clocks = <&syscrg JH7110_SYSCLK_WDT_APB>,
818 <&syscrg JH7110_SYSCLK_WDT_CORE>;
819 clock-names = "apb", "core";
820 resets = <&syscrg JH7110_SYSRST_WDT_APB>,
821 <&syscrg JH7110_SYSRST_WDT_CORE>;
822 };
823
824 mmc0: mmc@16010000 {
825 compatible = "starfive,jh7110-mmc";
826 reg = <0x0 0x16010000 0x0 0x10000>;
827 clocks = <&syscrg JH7110_SYSCLK_SDIO0_AHB>,
828 <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
829 clock-names = "biu","ciu";
830 resets = <&syscrg JH7110_SYSRST_SDIO0_AHB>;
831 reset-names = "reset";
832 interrupts = <74>;
833 fifo-depth = <32>;
834 fifo-watermark-aligned;
835 data-addr = <0>;
836 starfive,sysreg = <&sys_syscon 0x14 0x1a 0x7c000000>;
837 status = "disabled";
838 };
839
840 mmc1: mmc@16020000 {
841 compatible = "starfive,jh7110-mmc";
842 reg = <0x0 0x16020000 0x0 0x10000>;
843 clocks = <&syscrg JH7110_SYSCLK_SDIO1_AHB>,
844 <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
845 clock-names = "biu","ciu";
846 resets = <&syscrg JH7110_SYSRST_SDIO1_AHB>;
847 reset-names = "reset";
848 interrupts = <75>;
849 fifo-depth = <32>;
850 fifo-watermark-aligned;
851 data-addr = <0>;
852 starfive,sysreg = <&sys_syscon 0x9c 0x1 0x3e>;
853 status = "disabled";
854 };
855
856 gmac0: ethernet@16030000 {
857 compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
858 reg = <0x0 0x16030000 0x0 0x10000>;
859 clocks = <&aoncrg JH7110_AONCLK_GMAC0_AXI>,
860 <&aoncrg JH7110_AONCLK_GMAC0_AHB>,
861 <&syscrg JH7110_SYSCLK_GMAC0_PTP>,
862 <&aoncrg JH7110_AONCLK_GMAC0_TX_INV>,
863 <&syscrg JH7110_SYSCLK_GMAC0_GTXC>;
864 clock-names = "stmmaceth", "pclk", "ptp_ref",
865 "tx", "gtx";
866 resets = <&aoncrg JH7110_AONRST_GMAC0_AXI>,
867 <&aoncrg JH7110_AONRST_GMAC0_AHB>;
868 reset-names = "stmmaceth", "ahb";
869 interrupts = <7>, <6>, <5>;
870 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
871 rx-fifo-depth = <2048>;
872 tx-fifo-depth = <2048>;
873 snps,multicast-filter-bins = <64>;
874 snps,perfect-filter-entries = <8>;
875 snps,fixed-burst;
876 snps,no-pbl-x8;
877 snps,force_thresh_dma_mode;
878 snps,axi-config = <&stmmac_axi_setup>;
879 snps,tso;
880 snps,en-tx-lpi-clockgating;
881 snps,txpbl = <16>;
882 snps,rxpbl = <16>;
883 starfive,syscon = <&aon_syscon 0xc 0x12>;
884 status = "disabled";
885 };
886
887 gmac1: ethernet@16040000 {
888 compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
889 reg = <0x0 0x16040000 0x0 0x10000>;
890 clocks = <&syscrg JH7110_SYSCLK_GMAC1_AXI>,
891 <&syscrg JH7110_SYSCLK_GMAC1_AHB>,
892 <&syscrg JH7110_SYSCLK_GMAC1_PTP>,
893 <&syscrg JH7110_SYSCLK_GMAC1_TX_INV>,
894 <&syscrg JH7110_SYSCLK_GMAC1_GTXC>;
895 clock-names = "stmmaceth", "pclk", "ptp_ref",
896 "tx", "gtx";
897 resets = <&syscrg JH7110_SYSRST_GMAC1_AXI>,
898 <&syscrg JH7110_SYSRST_GMAC1_AHB>;
899 reset-names = "stmmaceth", "ahb";
900 interrupts = <78>, <77>, <76>;
901 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
902 rx-fifo-depth = <2048>;
903 tx-fifo-depth = <2048>;
904 snps,multicast-filter-bins = <64>;
905 snps,perfect-filter-entries = <8>;
906 snps,fixed-burst;
907 snps,no-pbl-x8;
908 snps,force_thresh_dma_mode;
909 snps,axi-config = <&stmmac_axi_setup>;
910 snps,tso;
911 snps,en-tx-lpi-clockgating;
912 snps,txpbl = <16>;
913 snps,rxpbl = <16>;
914 starfive,syscon = <&sys_syscon 0x90 0x2>;
915 status = "disabled";
916 };
917
918 dma: dma-controller@16050000 {
919 compatible = "starfive,jh7110-axi-dma";
920 reg = <0x0 0x16050000 0x0 0x10000>;
921 clocks = <&stgcrg JH7110_STGCLK_DMA1P_AXI>,
922 <&stgcrg JH7110_STGCLK_DMA1P_AHB>;
923 clock-names = "core-clk", "cfgr-clk";
924 resets = <&stgcrg JH7110_STGRST_DMA1P_AXI>,
925 <&stgcrg JH7110_STGRST_DMA1P_AHB>;
926 interrupts = <73>;
927 #dma-cells = <1>;
928 dma-channels = <4>;
929 snps,dma-masters = <1>;
930 snps,data-width = <3>;
931 snps,block-size = <65536 65536 65536 65536>;
932 snps,priority = <0 1 2 3>;
933 snps,axi-max-burst-len = <16>;
934 };
935
515 aoncrg: clock-controller@17000000 {
516 compatible = "starfive,jh7110-aoncrg";
517 reg = <0x0 0x17000000 0x0 0x10000>;
518 clocks = <&osc>, <&gmac0_rmii_refin>,
519 <&gmac0_rgmii_rxin>,
520 <&syscrg JH7110_SYSCLK_STG_AXIAHB>,
521 <&syscrg JH7110_SYSCLK_APB_BUS>,
522 <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>,
523 <&rtc_osc>;
524 clock-names = "osc", "gmac0_rmii_refin",
525 "gmac0_rgmii_rxin", "stg_axiahb",
526 "apb_bus", "gmac0_gtxclk",
527 "rtc_osc";
528 #clock-cells = <1>;
529 #reset-cells = <1>;
530 };
531
936 aoncrg: clock-controller@17000000 {
937 compatible = "starfive,jh7110-aoncrg";
938 reg = <0x0 0x17000000 0x0 0x10000>;
939 clocks = <&osc>, <&gmac0_rmii_refin>,
940 <&gmac0_rgmii_rxin>,
941 <&syscrg JH7110_SYSCLK_STG_AXIAHB>,
942 <&syscrg JH7110_SYSCLK_APB_BUS>,
943 <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>,
944 <&rtc_osc>;
945 clock-names = "osc", "gmac0_rmii_refin",
946 "gmac0_rgmii_rxin", "stg_axiahb",
947 "apb_bus", "gmac0_gtxclk",
948 "rtc_osc";
949 #clock-cells = <1>;
950 #reset-cells = <1>;
951 };
952
953 aon_syscon: syscon@17010000 {
954 compatible = "starfive,jh7110-aon-syscon", "syscon";
955 reg = <0x0 0x17010000 0x0 0x1000>;
956 #power-domain-cells = <1>;
957 };
958
532 aongpio: pinctrl@17020000 {
533 compatible = "starfive,jh7110-aon-pinctrl";
534 reg = <0x0 0x17020000 0x0 0x10000>;
535 resets = <&aoncrg JH7110_AONRST_IOMUX>;
536 interrupts = <85>;
537 interrupt-controller;
538 #interrupt-cells = <2>;
539 gpio-controller;
540 #gpio-cells = <2>;
541 };
542
543 pwrc: power-controller@17030000 {
544 compatible = "starfive,jh7110-pmu";
545 reg = <0x0 0x17030000 0x0 0x10000>;
546 interrupts = <111>;
547 #power-domain-cells = <1>;
548 };
959 aongpio: pinctrl@17020000 {
960 compatible = "starfive,jh7110-aon-pinctrl";
961 reg = <0x0 0x17020000 0x0 0x10000>;
962 resets = <&aoncrg JH7110_AONRST_IOMUX>;
963 interrupts = <85>;
964 interrupt-controller;
965 #interrupt-cells = <2>;
966 gpio-controller;
967 #gpio-cells = <2>;
968 };
969
970 pwrc: power-controller@17030000 {
971 compatible = "starfive,jh7110-pmu";
972 reg = <0x0 0x17030000 0x0 0x10000>;
973 interrupts = <111>;
974 #power-domain-cells = <1>;
975 };
976
977 ispcrg: clock-controller@19810000 {
978 compatible = "starfive,jh7110-ispcrg";
979 reg = <0x0 0x19810000 0x0 0x10000>;
980 clocks = <&syscrg JH7110_SYSCLK_ISP_TOP_CORE>,
981 <&syscrg JH7110_SYSCLK_ISP_TOP_AXI>,
982 <&syscrg JH7110_SYSCLK_NOC_BUS_ISP_AXI>,
983 <&dvp_clk>;
984 clock-names = "isp_top_core", "isp_top_axi",
985 "noc_bus_isp_axi", "dvp_clk";
986 resets = <&syscrg JH7110_SYSRST_ISP_TOP>,
987 <&syscrg JH7110_SYSRST_ISP_TOP_AXI>,
988 <&syscrg JH7110_SYSRST_NOC_BUS_ISP_AXI>;
989 #clock-cells = <1>;
990 #reset-cells = <1>;
991 power-domains = <&pwrc JH7110_PD_ISP>;
992 };
993
994 voutcrg: clock-controller@295c0000 {
995 compatible = "starfive,jh7110-voutcrg";
996 reg = <0x0 0x295c0000 0x0 0x10000>;
997 clocks = <&syscrg JH7110_SYSCLK_VOUT_SRC>,
998 <&syscrg JH7110_SYSCLK_VOUT_TOP_AHB>,
999 <&syscrg JH7110_SYSCLK_VOUT_TOP_AXI>,
1000 <&syscrg JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK>,
1001 <&syscrg JH7110_SYSCLK_I2STX0_BCLK>,
1002 <&hdmitx0_pixelclk>;
1003 clock-names = "vout_src", "vout_top_ahb",
1004 "vout_top_axi", "vout_top_hdmitx0_mclk",
1005 "i2stx0_bclk", "hdmitx0_pixelclk";
1006 resets = <&syscrg JH7110_SYSRST_VOUT_TOP_SRC>;
1007 #clock-cells = <1>;
1008 #reset-cells = <1>;
1009 power-domains = <&pwrc JH7110_PD_VOUT>;
1010 };
549 };
550};
1011 };
1012};