r9a07g043f.dtsi (7ae9fb1b7ecbb5d85d07857943f677fd1a559b18) r9a07g043f.dtsi (a38b1061d327c120844e5dc0217191b06ce3b25f)
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ/Five SoC
4 *
5 * Copyright (C) 2022 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/irq.h>

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24 reg = <0x0>;
25 status = "okay";
26 riscv,isa = "rv64imafdc";
27 mmu-type = "riscv,sv39";
28 i-cache-size = <0x8000>;
29 i-cache-line-size = <0x40>;
30 d-cache-size = <0x8000>;
31 d-cache-line-size = <0x40>;
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ/Five SoC
4 *
5 * Copyright (C) 2022 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/irq.h>

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24 reg = <0x0>;
25 status = "okay";
26 riscv,isa = "rv64imafdc";
27 mmu-type = "riscv,sv39";
28 i-cache-size = <0x8000>;
29 i-cache-line-size = <0x40>;
30 d-cache-size = <0x8000>;
31 d-cache-line-size = <0x40>;
32 next-level-cache = <&l2cache>;
32 clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
33 operating-points-v2 = <&cluster0_opp>;
34
35 cpu0_intc: interrupt-controller {
36 #interrupt-cells = <1>;
37 compatible = "riscv,cpu-intc";
38 interrupt-controller;
39 };

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51 riscv,ndev = <511>;
52 interrupt-controller;
53 reg = <0x0 0x12c00000 0 0x400000>;
54 clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
55 power-domains = <&cpg>;
56 resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
57 interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
58 };
33 clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
34 operating-points-v2 = <&cluster0_opp>;
35
36 cpu0_intc: interrupt-controller {
37 #interrupt-cells = <1>;
38 compatible = "riscv,cpu-intc";
39 interrupt-controller;
40 };

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52 riscv,ndev = <511>;
53 interrupt-controller;
54 reg = <0x0 0x12c00000 0 0x400000>;
55 clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
56 power-domains = <&cpg>;
57 resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
58 interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
59 };
60
61 l2cache: cache-controller@13400000 {
62 compatible = "andestech,ax45mp-cache", "cache";
63 reg = <0x0 0x13400000 0x0 0x100000>;
64 interrupts = <SOC_PERIPHERAL_IRQ(476) IRQ_TYPE_LEVEL_HIGH>;
65 cache-size = <0x40000>;
66 cache-line-size = <64>;
67 cache-sets = <1024>;
68 cache-unified;
69 cache-level = <2>;
70 };
59};
71};