r9a07g043f.dtsi (5d2d4a9f603a47403395408f64b1261ca61f6d50) r9a07g043f.dtsi (bfc1d3a9011a35e673b026055194dc09e734742a)
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ/Five SoC
4 *
5 * Copyright (C) 2022 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/irq.h>

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19
20 cpu0: cpu@0 {
21 compatible = "andestech,ax45mp", "riscv";
22 device_type = "cpu";
23 #cooling-cells = <2>;
24 reg = <0x0>;
25 status = "okay";
26 riscv,isa = "rv64imafdc";
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ/Five SoC
4 *
5 * Copyright (C) 2022 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/irq.h>

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19
20 cpu0: cpu@0 {
21 compatible = "andestech,ax45mp", "riscv";
22 device_type = "cpu";
23 #cooling-cells = <2>;
24 reg = <0x0>;
25 status = "okay";
26 riscv,isa = "rv64imafdc";
27 riscv,isa-base = "rv64i";
28 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
29 "zicntr", "zicsr", "zifencei",
30 "zihpm";
27 mmu-type = "riscv,sv39";
28 i-cache-size = <0x8000>;
29 i-cache-line-size = <0x40>;
30 d-cache-size = <0x8000>;
31 d-cache-line-size = <0x40>;
32 next-level-cache = <&l2cache>;
33 clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
34 operating-points-v2 = <&cluster0_opp>;

--- 38 unchanged lines hidden --- 		31 mmu-type = "riscv,sv39";
32 i-cache-size = <0x8000>;
33 i-cache-line-size = <0x40>;
34 d-cache-size = <0x8000>;
35 d-cache-line-size = <0x40>;
36 next-level-cache = <&l2cache>;
37 clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
38 operating-points-v2 = <&cluster0_opp>;

--- 38 unchanged lines hidden ---