| fsl_rio.c (93e2cbd24e71f5eedf6e49e075973fda9b2135e8) | fsl_rio.c (af84ca38aff94061dd0711edbb99b0900a9c28fd) |
|---|---|
| 1/* 2 * Freescale MPC85xx/MPC86xx RapidIO support 3 * 4 * Copyright 2009 Sysgo AG 5 * Thomas Moll <thomas.moll@sysgo.com> 6 * - fixed maintenance access routines, check for aligned access 7 * 8 * Copyright 2009 Integrated Device Technology, Inc. --- 36 unchanged lines hidden (view full) --- 45#define IRQ_RIO_BELL(m) (((struct rio_priv *)(m->priv))->bellirq) 46#define IRQ_RIO_TX(m) (((struct rio_priv *)(m->priv))->txirq) 47#define IRQ_RIO_RX(m) (((struct rio_priv *)(m->priv))->rxirq) 48#define IRQ_RIO_PW(m) (((struct rio_priv *)(m->priv))->pwirq) 49 50#define RIO_ATMU_REGS_OFFSET 0x10c00 51#define RIO_P_MSG_REGS_OFFSET 0x11000 52#define RIO_S_MSG_REGS_OFFSET 0x13000 | 1/* 2 * Freescale MPC85xx/MPC86xx RapidIO support 3 * 4 * Copyright 2009 Sysgo AG 5 * Thomas Moll <thomas.moll@sysgo.com> 6 * - fixed maintenance access routines, check for aligned access 7 * 8 * Copyright 2009 Integrated Device Technology, Inc. --- 36 unchanged lines hidden (view full) --- 45#define IRQ_RIO_BELL(m) (((struct rio_priv *)(m->priv))->bellirq) 46#define IRQ_RIO_TX(m) (((struct rio_priv *)(m->priv))->txirq) 47#define IRQ_RIO_RX(m) (((struct rio_priv *)(m->priv))->rxirq) 48#define IRQ_RIO_PW(m) (((struct rio_priv *)(m->priv))->pwirq) 49 50#define RIO_ATMU_REGS_OFFSET 0x10c00 51#define RIO_P_MSG_REGS_OFFSET 0x11000 52#define RIO_S_MSG_REGS_OFFSET 0x13000 |
| 53#define RIO_GCCSR 0x13c |
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| 53#define RIO_ESCSR 0x158 54#define RIO_CCSR 0x15c 55#define RIO_LTLEDCSR 0x0608 56#define RIO_LTLEDCSR_IER 0x80000000 57#define RIO_LTLEDCSR_PRT 0x01000000 58#define RIO_LTLEECSR 0x060c 59#define RIO_EPWISR 0x10010 60#define RIO_ISR_AACR 0x10120 --- 1405 unchanged lines hidden (view full) --- 1466 strcpy(port->name, "RIO0 mport"); 1467 1468 priv->dev = &dev->dev; 1469 1470 port->ops = ops; 1471 port->host_deviceid = fsl_rio_get_hdid(port->id); 1472 1473 port->priv = priv; | 54#define RIO_ESCSR 0x158 55#define RIO_CCSR 0x15c 56#define RIO_LTLEDCSR 0x0608 57#define RIO_LTLEDCSR_IER 0x80000000 58#define RIO_LTLEDCSR_PRT 0x01000000 59#define RIO_LTLEECSR 0x060c 60#define RIO_EPWISR 0x10010 61#define RIO_ISR_AACR 0x10120 --- 1405 unchanged lines hidden (view full) --- 1467 strcpy(port->name, "RIO0 mport"); 1468 1469 priv->dev = &dev->dev; 1470 1471 port->ops = ops; 1472 port->host_deviceid = fsl_rio_get_hdid(port->id); 1473 1474 port->priv = priv; |
| 1475 port->phys_efptr = 0x100; |
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| 1474 rio_register_mport(port); 1475 1476 priv->regs_win = ioremap(regs.start, regs.end - regs.start + 1); 1477 rio_regs_win = priv->regs_win; 1478 1479 /* Probe the master port phy type */ 1480 ccsr = in_be32(priv->regs_win + RIO_CCSR); 1481 port->phy_type = (ccsr & 1) ? RIO_PHY_SERIAL : RIO_PHY_PARALLEL; --- 31 unchanged lines hidden (view full) --- 1513 } 1514 fsl_rio_info(&dev->dev, ccsr); 1515 1516 port->sys_size = (in_be32((priv->regs_win + RIO_PEF_CAR)) 1517 & RIO_PEF_CTLS) >> 4; 1518 dev_info(&dev->dev, "RapidIO Common Transport System size: %d\n", 1519 port->sys_size ? 65536 : 256); 1520 | 1476 rio_register_mport(port); 1477 1478 priv->regs_win = ioremap(regs.start, regs.end - regs.start + 1); 1479 rio_regs_win = priv->regs_win; 1480 1481 /* Probe the master port phy type */ 1482 ccsr = in_be32(priv->regs_win + RIO_CCSR); 1483 port->phy_type = (ccsr & 1) ? RIO_PHY_SERIAL : RIO_PHY_PARALLEL; --- 31 unchanged lines hidden (view full) --- 1515 } 1516 fsl_rio_info(&dev->dev, ccsr); 1517 1518 port->sys_size = (in_be32((priv->regs_win + RIO_PEF_CAR)) 1519 & RIO_PEF_CTLS) >> 4; 1520 dev_info(&dev->dev, "RapidIO Common Transport System size: %d\n", 1521 port->sys_size ? 65536 : 256); 1522 |
| 1523 if (port->host_deviceid >= 0) 1524 out_be32(priv->regs_win + RIO_GCCSR, RIO_PORT_GEN_HOST | 1525 RIO_PORT_GEN_MASTER | RIO_PORT_GEN_DISCOVERED); 1526 else 1527 out_be32(priv->regs_win + RIO_GCCSR, 0x00000000); 1528 |
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| 1521 priv->atmu_regs = (struct rio_atmu_regs *)(priv->regs_win 1522 + RIO_ATMU_REGS_OFFSET); 1523 priv->maint_atmu_regs = priv->atmu_regs + 1; 1524 priv->dbell_atmu_regs = priv->atmu_regs + 2; 1525 priv->msg_regs = (struct rio_msg_regs *)(priv->regs_win + 1526 ((port->phy_type == RIO_PHY_SERIAL) ? 1527 RIO_S_MSG_REGS_OFFSET : RIO_P_MSG_REGS_OFFSET)); 1528 --- 78 unchanged lines hidden --- | 1529 priv->atmu_regs = (struct rio_atmu_regs *)(priv->regs_win 1530 + RIO_ATMU_REGS_OFFSET); 1531 priv->maint_atmu_regs = priv->atmu_regs + 1; 1532 priv->dbell_atmu_regs = priv->atmu_regs + 2; 1533 priv->msg_regs = (struct rio_msg_regs *)(priv->regs_win + 1534 ((port->phy_type == RIO_PHY_SERIAL) ? 1535 RIO_S_MSG_REGS_OFFSET : RIO_P_MSG_REGS_OFFSET)); 1536 --- 78 unchanged lines hidden --- |