fsl_pci.c (b3bbcc5d1da1b654091dad15980b3d58fdae0fc6) fsl_pci.c (688de017efaab8a7764ab2c05ce7128d0361023b)
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * MPC83xx/85xx/86xx PCI/PCIE support routing.
4 *
5 * Copyright 2007-2012 Freescale Semiconductor, Inc.
6 * Copyright 2008-2009 MontaVista Software, Inc.
7 *
8 * Initial author: Xianghua Xiao <x.xiao@freescale.com>

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176 }
177
178 return i;
179}
180
181static bool is_kdump(void)
182{
183 struct device_node *node;
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * MPC83xx/85xx/86xx PCI/PCIE support routing.
4 *
5 * Copyright 2007-2012 Freescale Semiconductor, Inc.
6 * Copyright 2008-2009 MontaVista Software, Inc.
7 *
8 * Initial author: Xianghua Xiao <x.xiao@freescale.com>

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176 }
177
178 return i;
179}
180
181static bool is_kdump(void)
182{
183 struct device_node *node;
184 bool ret;
184
185 node = of_find_node_by_type(NULL, "memory");
186 if (!node) {
187 WARN_ON_ONCE(1);
188 return false;
189 }
190
185
186 node = of_find_node_by_type(NULL, "memory");
187 if (!node) {
188 WARN_ON_ONCE(1);
189 return false;
190 }
191
191 return of_property_read_bool(node, "linux,usable-memory");
192 ret = of_property_read_bool(node, "linux,usable-memory");
193 of_node_put(node);
194
195 return ret;
192}
193
194/* atmu setup for fsl pci/pcie controller */
195static void setup_pci_atmu(struct pci_controller *hose)
196{
197 struct ccsr_pci __iomem *pci = hose->private_data;
198 int i, j, n, mem_log, win_idx = 3, start_idx = 1, end_idx = 4;
199 u64 mem, sz, paddr_hi = 0;

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934
935 return base;
936 }
937#endif
938
939 return 0;
940}
941
196}
197
198/* atmu setup for fsl pci/pcie controller */
199static void setup_pci_atmu(struct pci_controller *hose)
200{
201 struct ccsr_pci __iomem *pci = hose->private_data;
202 int i, j, n, mem_log, win_idx = 3, start_idx = 1, end_idx = 4;
203 u64 mem, sz, paddr_hi = 0;

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938
939 return base;
940 }
941#endif
942
943 return 0;
944}
945
942#ifdef CONFIG_E500
946#ifdef CONFIG_PPC_E500
943static int mcheck_handle_load(struct pt_regs *regs, u32 inst)
944{
945 unsigned int rd, ra, rb, d;
946
947 rd = get_rt(inst);
948 ra = get_ra(inst);
949 rb = get_rb(inst);
950 d = get_d(inst);

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1137 /*
1138 * If there's no PCI host bridge with ISA, arbitrarily
1139 * designate one as primary. This can go away once
1140 * various bugs with primary-less systems are fixed.
1141 */
1142 for_each_matching_node(np, pci_ids) {
1143 if (of_device_is_available(np)) {
1144 fsl_pci_primary = np;
947static int mcheck_handle_load(struct pt_regs *regs, u32 inst)
948{
949 unsigned int rd, ra, rb, d;
950
951 rd = get_rt(inst);
952 ra = get_ra(inst);
953 rb = get_rb(inst);
954 d = get_d(inst);

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1141 /*
1142 * If there's no PCI host bridge with ISA, arbitrarily
1143 * designate one as primary. This can go away once
1144 * various bugs with primary-less systems are fixed.
1145 */
1146 for_each_matching_node(np, pci_ids) {
1147 if (of_device_is_available(np)) {
1148 fsl_pci_primary = np;
1145 of_node_put(np);
1146 return;
1147 }
1148 }
1149}
1150
1151#ifdef CONFIG_PM_SLEEP
1152static irqreturn_t fsl_pci_pme_handle(int irq, void *dev_id)
1153{

--- 197 unchanged lines hidden --- 		1149 return;
1150 }
1151 }
1152}
1153
1154#ifdef CONFIG_PM_SLEEP
1155static irqreturn_t fsl_pci_pme_handle(int irq, void *dev_id)
1156{

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