fsl_pci.c (08871c097ea5a11c95146ba8310272571d2bbfc4) fsl_pci.c (0e47ff1ce65bbd0b12a9421a2756b26987ea5083)
1/*
2 * MPC83xx/85xx/86xx PCI/PCIE support routing.
3 *
4 * Copyright 2007-2011 Freescale Semiconductor, Inc.
5 * Copyright 2008-2009 MontaVista Software, Inc.
6 *
7 * Initial author: Xianghua Xiao <x.xiao@freescale.com>
8 * Recode: ZHANG WEI <wei.zhang@freescale.com>

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33#include <asm/machdep.h>
34#include <sysdev/fsl_soc.h>
35#include <sysdev/fsl_pci.h>
36
37static int fsl_pcie_bus_fixup, is_mpc83xx_pci;
38
39static void __init quirk_fsl_pcie_header(struct pci_dev *dev)
40{
1/*
2 * MPC83xx/85xx/86xx PCI/PCIE support routing.
3 *
4 * Copyright 2007-2011 Freescale Semiconductor, Inc.
5 * Copyright 2008-2009 MontaVista Software, Inc.
6 *
7 * Initial author: Xianghua Xiao <x.xiao@freescale.com>
8 * Recode: ZHANG WEI <wei.zhang@freescale.com>

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33#include <asm/machdep.h>
34#include <sysdev/fsl_soc.h>
35#include <sysdev/fsl_pci.h>
36
37static int fsl_pcie_bus_fixup, is_mpc83xx_pci;
38
39static void __init quirk_fsl_pcie_header(struct pci_dev *dev)
40{
41 u8 progif;
42
43 /* if we aren't a PCIe don't bother */
44 if (!pci_find_capability(dev, PCI_CAP_ID_EXP))
45 return;
46
41 /* if we aren't a PCIe don't bother */
42 if (!pci_find_capability(dev, PCI_CAP_ID_EXP))
43 return;
44
47 /* if we aren't in host mode don't bother */
48 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
49 if (progif & 0x1)
50 return;
51
52 dev->class = PCI_CLASS_BRIDGE_PCI << 8;
53 fsl_pcie_bus_fixup = 1;
54 return;
55}
56
57static int __init fsl_pcie_check_link(struct pci_controller *hose)
58{
59 u32 val;

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325}
326
327int __init fsl_add_bridge(struct device_node *dev, int is_primary)
328{
329 int len;
330 struct pci_controller *hose;
331 struct resource rsrc;
332 const int *bus_range;
45 dev->class = PCI_CLASS_BRIDGE_PCI << 8;
46 fsl_pcie_bus_fixup = 1;
47 return;
48}
49
50static int __init fsl_pcie_check_link(struct pci_controller *hose)
51{
52 u32 val;

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318}
319
320int __init fsl_add_bridge(struct device_node *dev, int is_primary)
321{
322 int len;
323 struct pci_controller *hose;
324 struct resource rsrc;
325 const int *bus_range;
333 u8 progif;
334
335 if (!of_device_is_available(dev)) {
336 pr_warning("%s: disabled\n", dev->full_name);
337 return -ENODEV;
338 }
339
340 pr_debug("Adding PCI host bridge %s\n", dev->full_name);
341

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346 }
347
348 /* Get bus range if any */
349 bus_range = of_get_property(dev, "bus-range", &len);
350 if (bus_range == NULL || len < 2 * sizeof(int))
351 printk(KERN_WARNING "Can't get bus-range for %s, assume"
352 " bus 0\n", dev->full_name);
353
326
327 if (!of_device_is_available(dev)) {
328 pr_warning("%s: disabled\n", dev->full_name);
329 return -ENODEV;
330 }
331
332 pr_debug("Adding PCI host bridge %s\n", dev->full_name);
333

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338 }
339
340 /* Get bus range if any */
341 bus_range = of_get_property(dev, "bus-range", &len);
342 if (bus_range == NULL || len < 2 * sizeof(int))
343 printk(KERN_WARNING "Can't get bus-range for %s, assume"
344 " bus 0\n", dev->full_name);
345
354 ppc_pci_add_flags(PPC_PCI_REASSIGN_ALL_BUS);
346 pci_add_flags(PCI_REASSIGN_ALL_BUS);
355 hose = pcibios_alloc_controller(dev);
356 if (!hose)
357 return -ENOMEM;
358
359 hose->first_busno = bus_range ? bus_range[0] : 0x0;
360 hose->last_busno = bus_range ? bus_range[1] : 0xff;
361
362 setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
363 PPC_INDIRECT_TYPE_BIG_ENDIAN);
347 hose = pcibios_alloc_controller(dev);
348 if (!hose)
349 return -ENOMEM;
350
351 hose->first_busno = bus_range ? bus_range[0] : 0x0;
352 hose->last_busno = bus_range ? bus_range[1] : 0xff;
353
354 setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
355 PPC_INDIRECT_TYPE_BIG_ENDIAN);
364
365 early_read_config_byte(hose, 0, 0, PCI_CLASS_PROG, &progif);
366 if ((progif & 1) == 1) {
367 /* unmap cfg_data & cfg_addr separately if not on same page */
368 if (((unsigned long)hose->cfg_data & PAGE_MASK) !=
369 ((unsigned long)hose->cfg_addr & PAGE_MASK))
370 iounmap(hose->cfg_data);
371 iounmap(hose->cfg_addr);
372 pcibios_free_controller(hose);
373 return 0;
374 }
375
376 setup_pci_cmd(hose);
377
378 /* check PCI express link status */
379 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
380 hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG |
381 PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
382 if (fsl_pcie_check_link(hose))
383 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;

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395 /* This also maps the I/O region and sets isa_io/mem_base */
396 pci_process_bridge_OF_ranges(hose, dev, is_primary);
397
398 /* Setup PEX window registers */
399 setup_pci_atmu(hose, &rsrc);
400
401 return 0;
402}
356 setup_pci_cmd(hose);
357
358 /* check PCI express link status */
359 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
360 hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG |
361 PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
362 if (fsl_pcie_check_link(hose))
363 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;

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375 /* This also maps the I/O region and sets isa_io/mem_base */
376 pci_process_bridge_OF_ranges(hose, dev, is_primary);
377
378 /* Setup PEX window registers */
379 setup_pci_atmu(hose, &rsrc);
380
381 return 0;
382}
383
384DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8548E, quirk_fsl_pcie_header);
385DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8548, quirk_fsl_pcie_header);
386DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8543E, quirk_fsl_pcie_header);
387DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8543, quirk_fsl_pcie_header);
388DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8547E, quirk_fsl_pcie_header);
389DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8545E, quirk_fsl_pcie_header);
390DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8545, quirk_fsl_pcie_header);
391DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8569E, quirk_fsl_pcie_header);
392DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8569, quirk_fsl_pcie_header);
393DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8568E, quirk_fsl_pcie_header);
394DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8568, quirk_fsl_pcie_header);
395DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8567E, quirk_fsl_pcie_header);
396DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8567, quirk_fsl_pcie_header);
397DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8533E, quirk_fsl_pcie_header);
398DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8533, quirk_fsl_pcie_header);
399DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8544E, quirk_fsl_pcie_header);
400DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8544, quirk_fsl_pcie_header);
401DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8572E, quirk_fsl_pcie_header);
402DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8572, quirk_fsl_pcie_header);
403DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8536E, quirk_fsl_pcie_header);
404DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8536, quirk_fsl_pcie_header);
405DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8641, quirk_fsl_pcie_header);
406DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8641D, quirk_fsl_pcie_header);
407DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8610, quirk_fsl_pcie_header);
408DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1011E, quirk_fsl_pcie_header);
409DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1011, quirk_fsl_pcie_header);
410DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1013E, quirk_fsl_pcie_header);
411DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1013, quirk_fsl_pcie_header);
412DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1020E, quirk_fsl_pcie_header);
413DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1020, quirk_fsl_pcie_header);
414DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1021E, quirk_fsl_pcie_header);
415DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1021, quirk_fsl_pcie_header);
416DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1022E, quirk_fsl_pcie_header);
417DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1022, quirk_fsl_pcie_header);
418DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2010E, quirk_fsl_pcie_header);
419DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2010, quirk_fsl_pcie_header);
420DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2020E, quirk_fsl_pcie_header);
421DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2020, quirk_fsl_pcie_header);
422DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2040E, quirk_fsl_pcie_header);
423DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2040, quirk_fsl_pcie_header);
424DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P3041E, quirk_fsl_pcie_header);
425DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P3041, quirk_fsl_pcie_header);
426DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P4040E, quirk_fsl_pcie_header);
427DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P4040, quirk_fsl_pcie_header);
428DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P4080E, quirk_fsl_pcie_header);
429DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P4080, quirk_fsl_pcie_header);
430DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P5010E, quirk_fsl_pcie_header);
431DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P5010, quirk_fsl_pcie_header);
432DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P5020E, quirk_fsl_pcie_header);
433DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P5020, quirk_fsl_pcie_header);
403#endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */
404
434#endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */
435
405DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_pcie_header);
406
407#if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x)
436#if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x)
437DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8308, quirk_fsl_pcie_header);
438DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8314E, quirk_fsl_pcie_header);
439DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8314, quirk_fsl_pcie_header);
440DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8315E, quirk_fsl_pcie_header);
441DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8315, quirk_fsl_pcie_header);
442DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8377E, quirk_fsl_pcie_header);
443DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8377, quirk_fsl_pcie_header);
444DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8378E, quirk_fsl_pcie_header);
445DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8378, quirk_fsl_pcie_header);
446
408struct mpc83xx_pcie_priv {
409 void __iomem *cfg_type0;
410 void __iomem *cfg_type1;
411 u32 dev_base;
412};
413
414struct pex_inbound_window {
415 u32 ar;

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635
636 /* Get bus range if any */
637 bus_range = of_get_property(dev, "bus-range", &len);
638 if (bus_range == NULL || len < 2 * sizeof(int)) {
639 printk(KERN_WARNING "Can't get bus-range for %s, assume"
640 " bus 0\n", dev->full_name);
641 }
642
447struct mpc83xx_pcie_priv {
448 void __iomem *cfg_type0;
449 void __iomem *cfg_type1;
450 u32 dev_base;
451};
452
453struct pex_inbound_window {
454 u32 ar;

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674
675 /* Get bus range if any */
676 bus_range = of_get_property(dev, "bus-range", &len);
677 if (bus_range == NULL || len < 2 * sizeof(int)) {
678 printk(KERN_WARNING "Can't get bus-range for %s, assume"
679 " bus 0\n", dev->full_name);
680 }
681
643 ppc_pci_add_flags(PPC_PCI_REASSIGN_ALL_BUS);
682 pci_add_flags(PCI_REASSIGN_ALL_BUS);
644 hose = pcibios_alloc_controller(dev);
645 if (!hose)
646 return -ENOMEM;
647
648 hose->first_busno = bus_range ? bus_range[0] : 0;
649 hose->last_busno = bus_range ? bus_range[1] : 0xff;
650
651 if (of_device_is_compatible(dev, "fsl,mpc8314-pcie")) {

--- 63 unchanged lines hidden --- 		683 hose = pcibios_alloc_controller(dev);
684 if (!hose)
685 return -ENOMEM;
686
687 hose->first_busno = bus_range ? bus_range[0] : 0;
688 hose->last_busno = bus_range ? bus_range[1] : 0xff;
689
690 if (of_device_is_compatible(dev, "fsl,mpc8314-pcie")) {

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