| cache.S (aaccf3c97418f169afdbb5855e9cbcbda34e90fd) | cache.S (d7cceda96badc1bd444cff27ab9c375a1277c1e3) |
|---|---|
| 1/* 2 * This file contains low-level cache management functions 3 * used for sleep and CPU speed changes on Apple machines. 4 * (In fact the only thing that is Apple-specific is that we assume 5 * that we can read from ROM at physical address 0xfff00000.) 6 * 7 * Copyright (C) 2004 Paul Mackerras (paulus@samba.org) and 8 * Benjamin Herrenschmidt (benh@kernel.crashing.org) --- 14 unchanged lines hidden (view full) --- 23 * Flush and disable all data caches (dL1, L2, L3). This is used 24 * when going to sleep, when doing a PMU based cpufreq transition, 25 * or when "offlining" a CPU on SMP machines. This code is over 26 * paranoid, but I've had enough issues with various CPU revs and 27 * bugs that I decided it was worth being over cautious 28 */ 29 30_GLOBAL(flush_disable_caches) | 1/* 2 * This file contains low-level cache management functions 3 * used for sleep and CPU speed changes on Apple machines. 4 * (In fact the only thing that is Apple-specific is that we assume 5 * that we can read from ROM at physical address 0xfff00000.) 6 * 7 * Copyright (C) 2004 Paul Mackerras (paulus@samba.org) and 8 * Benjamin Herrenschmidt (benh@kernel.crashing.org) --- 14 unchanged lines hidden (view full) --- 23 * Flush and disable all data caches (dL1, L2, L3). This is used 24 * when going to sleep, when doing a PMU based cpufreq transition, 25 * or when "offlining" a CPU on SMP machines. This code is over 26 * paranoid, but I've had enough issues with various CPU revs and 27 * bugs that I decided it was worth being over cautious 28 */ 29 30_GLOBAL(flush_disable_caches) |
| 31#ifndef CONFIG_6xx | 31#ifndef CONFIG_PPC_BOOK3S_32 |
| 32 blr 33#else 34BEGIN_FTR_SECTION 35 b flush_disable_745x 36END_FTR_SECTION_IFSET(CPU_FTR_SPEC7450) 37BEGIN_FTR_SECTION 38 b flush_disable_75x 39END_FTR_SECTION_IFSET(CPU_FTR_L2CR) --- 311 unchanged lines hidden (view full) --- 3516: mfspr r0,SPRN_HID0 /* now disable the L1 data cache */ 352 rlwinm r0,r0,0,~HID0_DCE 353 mtspr SPRN_HID0,r0 354 sync 355 isync 356 mtmsr r11 /* restore DR and EE */ 357 isync 358 blr | 32 blr 33#else 34BEGIN_FTR_SECTION 35 b flush_disable_745x 36END_FTR_SECTION_IFSET(CPU_FTR_SPEC7450) 37BEGIN_FTR_SECTION 38 b flush_disable_75x 39END_FTR_SECTION_IFSET(CPU_FTR_L2CR) --- 311 unchanged lines hidden (view full) --- 3516: mfspr r0,SPRN_HID0 /* now disable the L1 data cache */ 352 rlwinm r0,r0,0,~HID0_DCE 353 mtspr SPRN_HID0,r0 354 sync 355 isync 356 mtmsr r11 /* restore DR and EE */ 357 isync 358 blr |
| 359#endif /* CONFIG_6xx */ | 359#endif /* CONFIG_PPC_BOOK3S_32 */ |