hugetlbpage.c (0356656284ca750f882b7eb81b9612bdbc90b2c4) hugetlbpage.c (1e03c7e2ea83b0acac7934e55943d1d4354baa43)
1/*
2 * PPC Huge TLB Page Support for Kernel.
3 *
4 * Copyright (C) 2003 David Gibson, IBM Corporation.
5 * Copyright (C) 2011 Becky Bruce, Freescale Semiconductor
6 *
7 * Based on the IA-32 version:
8 * Copyright (C) 2002, Rohit Seth <rohit.seth@intel.com>

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65 if (pshift >= pdshift) {
66 cachep = PGT_CACHE(PTE_T_ORDER);
67 num_hugepd = 1 << (pshift - pdshift);
68 } else {
69 cachep = PGT_CACHE(pdshift - pshift);
70 num_hugepd = 1;
71 }
72
1/*
2 * PPC Huge TLB Page Support for Kernel.
3 *
4 * Copyright (C) 2003 David Gibson, IBM Corporation.
5 * Copyright (C) 2011 Becky Bruce, Freescale Semiconductor
6 *
7 * Based on the IA-32 version:
8 * Copyright (C) 2002, Rohit Seth <rohit.seth@intel.com>

--- 56 unchanged lines hidden (view full) ---

65 if (pshift >= pdshift) {
66 cachep = PGT_CACHE(PTE_T_ORDER);
67 num_hugepd = 1 << (pshift - pdshift);
68 } else {
69 cachep = PGT_CACHE(pdshift - pshift);
70 num_hugepd = 1;
71 }
72
73 new = kmem_cache_zalloc(cachep, pgtable_gfp_flags(mm, GFP_KERNEL));
73 new = kmem_cache_alloc(cachep, pgtable_gfp_flags(mm, GFP_KERNEL));
74
75 BUG_ON(pshift > HUGEPD_SHIFT_MASK);
76 BUG_ON((unsigned long)new & HUGEPD_SHIFT_MASK);
77
78 if (! new)
79 return -ENOMEM;
80
81 /*

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696
697 if (add_huge_page_size(1ULL << shift) < 0)
698 continue;
699 /*
700 * if we have pdshift and shift value same, we don't
701 * use pgt cache for hugepd.
702 */
703 if (pdshift > shift)
74
75 BUG_ON(pshift > HUGEPD_SHIFT_MASK);
76 BUG_ON((unsigned long)new & HUGEPD_SHIFT_MASK);
77
78 if (! new)
79 return -ENOMEM;
80
81 /*

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696
697 if (add_huge_page_size(1ULL << shift) < 0)
698 continue;
699 /*
700 * if we have pdshift and shift value same, we don't
701 * use pgt cache for hugepd.
702 */
703 if (pdshift > shift)
704 pgtable_cache_add(pdshift - shift, NULL);
704 pgtable_cache_add(pdshift - shift);
705#if defined(CONFIG_PPC_FSL_BOOK3E) || defined(CONFIG_PPC_8xx)
706 else
705#if defined(CONFIG_PPC_FSL_BOOK3E) || defined(CONFIG_PPC_8xx)
706 else
707 pgtable_cache_add(PTE_T_ORDER, NULL);
707 pgtable_cache_add(PTE_T_ORDER);
708#endif
709 }
710
711#if defined(CONFIG_PPC_FSL_BOOK3E) || defined(CONFIG_PPC_8xx)
712 /* Default hpage size = 4M on FSL_BOOK3E and 512k on 8xx */
713 if (mmu_psize_defs[MMU_PAGE_4M].shift)
714 HPAGE_SHIFT = mmu_psize_defs[MMU_PAGE_4M].shift;
715 else if (mmu_psize_defs[MMU_PAGE_512K].shift)

--- 187 unchanged lines hidden --- 		708#endif
709 }
710
711#if defined(CONFIG_PPC_FSL_BOOK3E) || defined(CONFIG_PPC_8xx)
712 /* Default hpage size = 4M on FSL_BOOK3E and 512k on 8xx */
713 if (mmu_psize_defs[MMU_PAGE_4M].shift)
714 HPAGE_SHIFT = mmu_psize_defs[MMU_PAGE_4M].shift;
715 else if (mmu_psize_defs[MMU_PAGE_512K].shift)

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