sstep.c (be96f63375a14ee8e690856ac77e579c75bd0bae) sstep.c (cf87c3f6b64791ce5d4c7e591c915065d31a162d)
1/*
2 * Single-step support.
3 *
4 * Copyright (C) 2004 Paul Mackerras <paulus@au.ibm.com>, IBM
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version

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595 else if (v1 > v2)
596 crval |= 4;
597 else
598 crval |= 2;
599 shift = (7 - crfld) * 4;
600 regs->ccr = (regs->ccr & ~(0xf << shift)) | (crval << shift);
601}
602
1/*
2 * Single-step support.
3 *
4 * Copyright (C) 2004 Paul Mackerras <paulus@au.ibm.com>, IBM
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version

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595 else if (v1 > v2)
596 crval |= 4;
597 else
598 crval |= 2;
599 shift = (7 - crfld) * 4;
600 regs->ccr = (regs->ccr & ~(0xf << shift)) | (crval << shift);
601}
602
603static int __kprobes trap_compare(long v1, long v2)
604{
605 int ret = 0;
606
607 if (v1 < v2)
608 ret |= 0x10;
609 else if (v1 > v2)
610 ret |= 0x08;
611 else
612 ret |= 0x04;
613 if ((unsigned long)v1 < (unsigned long)v2)
614 ret |= 0x02;
615 else if ((unsigned long)v1 > (unsigned long)v2)
616 ret |= 0x01;
617 return ret;
618}
619
603/*
604 * Elements of 32-bit rotate and mask instructions.
605 */
606#define MASK32(mb, me) ((0xffffffffUL >> (mb)) + \
607 ((signed long)-0x80000000L >> (me)) + ((me) >= (mb)))
608#ifdef __powerpc64__
609#define MASK64_L(mb) (~0UL >> (mb))
610#define MASK64_R(me) ((signed long)-0x8000000000000000L >> (me))

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664 imm += regs->nip;
665 if (instr & 1)
666 regs->link = truncate_if_32bit(regs->msr, regs->nip + 4);
667 imm = truncate_if_32bit(regs->msr, imm);
668 regs->nip = imm;
669 return 1;
670 case 19:
671 switch ((instr >> 1) & 0x3ff) {
620/*
621 * Elements of 32-bit rotate and mask instructions.
622 */
623#define MASK32(mb, me) ((0xffffffffUL >> (mb)) + \
624 ((signed long)-0x80000000L >> (me)) + ((me) >= (mb)))
625#ifdef __powerpc64__
626#define MASK64_L(mb) (~0UL >> (mb))
627#define MASK64_R(me) ((signed long)-0x8000000000000000L >> (me))

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681 imm += regs->nip;
682 if (instr & 1)
683 regs->link = truncate_if_32bit(regs->msr, regs->nip + 4);
684 imm = truncate_if_32bit(regs->msr, imm);
685 regs->nip = imm;
686 return 1;
687 case 19:
688 switch ((instr >> 1) & 0x3ff) {
689 case 0: /* mcrf */
690 rd = (instr >> 21) & 0x1c;
691 ra = (instr >> 16) & 0x1c;
692 val = (regs->ccr >> ra) & 0xf;
693 regs->ccr = (regs->ccr & ~(0xfUL << rd)) | (val << rd);
694 goto instr_done;
695
672 case 16: /* bclr */
673 case 528: /* bcctr */
674 op->type = BRANCH;
675 imm = (instr & 0x400)? regs->ctr: regs->link;
676 regs->nip = truncate_if_32bit(regs->msr, regs->nip + 4);
677 imm = truncate_if_32bit(regs->msr, imm);
678 if (instr & 1)
679 regs->link = regs->nip;

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740 if (!FULL_REGS(regs))
741 return 0;
742
743 rd = (instr >> 21) & 0x1f;
744 ra = (instr >> 16) & 0x1f;
745 rb = (instr >> 11) & 0x1f;
746
747 switch (opcode) {
696 case 16: /* bclr */
697 case 528: /* bcctr */
698 op->type = BRANCH;
699 imm = (instr & 0x400)? regs->ctr: regs->link;
700 regs->nip = truncate_if_32bit(regs->msr, regs->nip + 4);
701 imm = truncate_if_32bit(regs->msr, imm);
702 if (instr & 1)
703 regs->link = regs->nip;

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764 if (!FULL_REGS(regs))
765 return 0;
766
767 rd = (instr >> 21) & 0x1f;
768 ra = (instr >> 16) & 0x1f;
769 rb = (instr >> 11) & 0x1f;
770
771 switch (opcode) {
772#ifdef __powerpc64__
773 case 2: /* tdi */
774 if (rd & trap_compare(regs->gpr[ra], (short) instr))
775 goto trap;
776 goto instr_done;
777#endif
778 case 3: /* twi */
779 if (rd & trap_compare((int)regs->gpr[ra], (short) instr))
780 goto trap;
781 goto instr_done;
782
748 case 7: /* mulli */
749 regs->gpr[rd] = regs->gpr[ra] * (short) instr;
750 goto instr_done;
751
752 case 8: /* subfic */
753 imm = (short) instr;
754 add_with_carry(regs, rd, ~regs->gpr[ra], imm, 1);
755 goto instr_done;

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888 regs->gpr[ra] = val & MASK64_R(mb);
889 goto logical_done;
890 }
891 }
892#endif
893
894 case 31:
895 switch ((instr >> 1) & 0x3ff) {
783 case 7: /* mulli */
784 regs->gpr[rd] = regs->gpr[ra] * (short) instr;
785 goto instr_done;
786
787 case 8: /* subfic */
788 imm = (short) instr;
789 add_with_carry(regs, rd, ~regs->gpr[ra], imm, 1);
790 goto instr_done;

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923 regs->gpr[ra] = val & MASK64_R(mb);
924 goto logical_done;
925 }
926 }
927#endif
928
929 case 31:
930 switch ((instr >> 1) & 0x3ff) {
931 case 4: /* tw */
932 if (rd == 0x1f ||
933 (rd & trap_compare((int)regs->gpr[ra],
934 (int)regs->gpr[rb])))
935 goto trap;
936 goto instr_done;
937#ifdef __powerpc64__
938 case 68: /* td */
939 if (rd & trap_compare(regs->gpr[ra], regs->gpr[rb]))
940 goto trap;
941 goto instr_done;
942#endif
896 case 83: /* mfmsr */
897 if (regs->msr & MSR_PR)
898 goto priv;
899 op->type = MFMSR;
900 op->reg = rd;
901 return 0;
902 case 146: /* mtmsr */
903 if (regs->msr & MSR_PR)

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1264 op->reg = rd;
1265 return 0;
1266
1267 case 278: /* dcbt */
1268 op->type = MKOP(CACHEOP, DCBTST, 0);
1269 op->ea = xform_ea(instr, regs);
1270 op->reg = rd;
1271 return 0;
943 case 83: /* mfmsr */
944 if (regs->msr & MSR_PR)
945 goto priv;
946 op->type = MFMSR;
947 op->reg = rd;
948 return 0;
949 case 146: /* mtmsr */
950 if (regs->msr & MSR_PR)

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1311 op->reg = rd;
1312 return 0;
1313
1314 case 278: /* dcbt */
1315 op->type = MKOP(CACHEOP, DCBTST, 0);
1316 op->ea = xform_ea(instr, regs);
1317 op->reg = rd;
1318 return 0;
1319
1320 case 982: /* icbi */
1321 op->type = MKOP(CACHEOP, ICBI, 0);
1322 op->ea = xform_ea(instr, regs);
1323 return 0;
1272 }
1273 break;
1274 }
1275
1276 /*
1277 * Loads and stores.
1278 */
1279 op->type = UNKNOWN;

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1592 regs->nip = truncate_if_32bit(regs->msr, regs->nip + 4);
1593 return 1;
1594
1595 priv:
1596 op->type = INTERRUPT | 0x700;
1597 op->val = SRR1_PROGPRIV;
1598 return 0;
1599
1324 }
1325 break;
1326 }
1327
1328 /*
1329 * Loads and stores.
1330 */
1331 op->type = UNKNOWN;

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1644 regs->nip = truncate_if_32bit(regs->msr, regs->nip + 4);
1645 return 1;
1646
1647 priv:
1648 op->type = INTERRUPT | 0x700;
1649 op->val = SRR1_PROGPRIV;
1650 return 0;
1651
1652 trap:
1653 op->type = INTERRUPT | 0x700;
1654 op->val = SRR1_PROGTRAP;
1655 return 0;
1656
1600#ifdef CONFIG_PPC_FPU
1601 fpunavail:
1602 op->type = INTERRUPT | 0x800;
1603 return 0;
1604#endif
1605
1606#ifdef CONFIG_ALTIVEC
1607 vecunavail:

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1709 case DCBTST:
1710 if (op.reg == 0)
1711 prefetchw((void *) op.ea);
1712 break;
1713 case DCBT:
1714 if (op.reg == 0)
1715 prefetch((void *) op.ea);
1716 break;
1657#ifdef CONFIG_PPC_FPU
1658 fpunavail:
1659 op->type = INTERRUPT | 0x800;
1660 return 0;
1661#endif
1662
1663#ifdef CONFIG_ALTIVEC
1664 vecunavail:

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1766 case DCBTST:
1767 if (op.reg == 0)
1768 prefetchw((void *) op.ea);
1769 break;
1770 case DCBT:
1771 if (op.reg == 0)
1772 prefetch((void *) op.ea);
1773 break;
1774 case ICBI:
1775 __cacheop_user_asmx(op.ea, err, "icbi");
1776 break;
1717 }
1718 if (err)
1719 return 0;
1720 goto instr_done;
1721
1722 case LARX:
1723 if (regs->msr & MSR_LE)
1724 return 0;

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1778 if (err)
1779 return 0;
1780 goto instr_done;
1781
1782 case LARX:
1783 if (regs->msr & MSR_LE)
1784 return 0;

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