ldstfp.S (9095bf25ea08135a5b74875dd0e3eeaddc4218a0) | ldstfp.S (350779a29f11f80ac66a8b38a7718ad30f003f18) |
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1/* 2 * Floating-point, VMX/Altivec and VSX loads and stores 3 * for use in instruction emulation. 4 * 5 * Copyright 2010 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License --- 164 unchanged lines hidden (view full) --- 173 MTMSRD(r6) 174 isync 175 mr r3,r9 176 addi r1,r1,STKFRM 177 blr 178 EX_TABLE(2b,3b) 179 180#ifdef CONFIG_ALTIVEC | 1/* 2 * Floating-point, VMX/Altivec and VSX loads and stores 3 * for use in instruction emulation. 4 * 5 * Copyright 2010 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License --- 164 unchanged lines hidden (view full) --- 173 MTMSRD(r6) 174 isync 175 mr r3,r9 176 addi r1,r1,STKFRM 177 blr 178 EX_TABLE(2b,3b) 179 180#ifdef CONFIG_ALTIVEC |
181/* Get the contents of vrN into v0; N is in r3. */ | 181/* Get the contents of vrN into v0; N is in r3. Doesn't touch r3 or r4. */ |
182_GLOBAL(get_vr) 183 mflr r0 | 182_GLOBAL(get_vr) 183 mflr r0 |
184 rlwinm r3,r3,3,0xf8 | 184 rlwinm r6,r3,3,0xf8 |
185 bcl 20,31,1f 186 blr /* v0 is already in v0 */ 187 nop 188reg = 1 189 .rept 31 190 vor v0,reg,reg /* assembler doesn't know vmr? */ 191 blr 192reg = reg + 1 193 .endr 1941: mflr r5 | 185 bcl 20,31,1f 186 blr /* v0 is already in v0 */ 187 nop 188reg = 1 189 .rept 31 190 vor v0,reg,reg /* assembler doesn't know vmr? */ 191 blr 192reg = reg + 1 193 .endr 1941: mflr r5 |
195 add r5,r3,r5 | 195 add r5,r6,r5 |
196 mtctr r5 197 mtlr r0 198 bctr 199 | 196 mtctr r5 197 mtlr r0 198 bctr 199 |
200/* Put the contents of v0 into vrN; N is in r3. */ | 200/* Put the contents of v0 into vrN; N is in r3. Doesn't touch r3 or r4. */ |
201_GLOBAL(put_vr) 202 mflr r0 | 201_GLOBAL(put_vr) 202 mflr r0 |
203 rlwinm r3,r3,3,0xf8 | 203 rlwinm r6,r3,3,0xf8 |
204 bcl 20,31,1f 205 blr /* v0 is already in v0 */ 206 nop 207reg = 1 208 .rept 31 209 vor reg,v0,v0 210 blr 211reg = reg + 1 212 .endr 2131: mflr r5 | 204 bcl 20,31,1f 205 blr /* v0 is already in v0 */ 206 nop 207reg = 1 208 .rept 31 209 vor reg,v0,v0 210 blr 211reg = reg + 1 212 .endr 2131: mflr r5 |
214 add r5,r3,r5 | 214 add r5,r6,r5 |
215 mtctr r5 216 mtlr r0 217 bctr 218 219/* Load vector reg N from *p. N is in r3, p in r4. */ 220_GLOBAL(do_lvx) 221 PPC_STLU r1,-STKFRM(r1) 222 mflr r0 --- 85 unchanged lines hidden (view full) --- 308 .endr 3091: mflr r5 310 add r5,r3,r5 311 mtctr r5 312 mtlr r0 313 bctr 314 315/* Load VSX reg N from vector doubleword *p. N is in r3, p in r4. */ | 215 mtctr r5 216 mtlr r0 217 bctr 218 219/* Load vector reg N from *p. N is in r3, p in r4. */ 220_GLOBAL(do_lvx) 221 PPC_STLU r1,-STKFRM(r1) 222 mflr r0 --- 85 unchanged lines hidden (view full) --- 308 .endr 3091: mflr r5 310 add r5,r3,r5 311 mtctr r5 312 mtlr r0 313 bctr 314 315/* Load VSX reg N from vector doubleword *p. N is in r3, p in r4. */ |
316_GLOBAL(do_lxvd2x) | 316_GLOBAL(load_vsrn) |
317 PPC_STLU r1,-STKFRM(r1) 318 mflr r0 319 PPC_STL r0,STKFRM+PPC_LR_STKOFF(r1) 320 mfmsr r6 321 oris r7,r6,MSR_VSX@h 322 cmpwi cr7,r3,0 323 li r8,STKFRM-16 324 MTMSRD(r7) 325 isync 326 beq cr7,1f 327 STXVD2X(0,R1,R8) | 317 PPC_STLU r1,-STKFRM(r1) 318 mflr r0 319 PPC_STL r0,STKFRM+PPC_LR_STKOFF(r1) 320 mfmsr r6 321 oris r7,r6,MSR_VSX@h 322 cmpwi cr7,r3,0 323 li r8,STKFRM-16 324 MTMSRD(r7) 325 isync 326 beq cr7,1f 327 STXVD2X(0,R1,R8) |
3281: li r9,-EFAULT 3292: LXVD2X(0,R0,R4) 330 li r9,0 3313: beq cr7,4f | 3281: LXVD2X(0,R0,R4) 329#ifdef __LITTLE_ENDIAN__ 330 XXSWAPD(0,0) 331#endif 332 beq cr7,4f |
332 bl put_vsr 333 LXVD2X(0,R1,R8) 3344: PPC_LL r0,STKFRM+PPC_LR_STKOFF(r1) 335 mtlr r0 336 MTMSRD(r6) 337 isync | 333 bl put_vsr 334 LXVD2X(0,R1,R8) 3354: PPC_LL r0,STKFRM+PPC_LR_STKOFF(r1) 336 mtlr r0 337 MTMSRD(r6) 338 isync |
338 mr r3,r9 | |
339 addi r1,r1,STKFRM 340 blr | 339 addi r1,r1,STKFRM 340 blr |
341 EX_TABLE(2b,3b) | |
342 343/* Store VSX reg N to vector doubleword *p. N is in r3, p in r4. */ | 341 342/* Store VSX reg N to vector doubleword *p. N is in r3, p in r4. */ |
344_GLOBAL(do_stxvd2x) | 343_GLOBAL(store_vsrn) |
345 PPC_STLU r1,-STKFRM(r1) 346 mflr r0 347 PPC_STL r0,STKFRM+PPC_LR_STKOFF(r1) 348 mfmsr r6 349 oris r7,r6,MSR_VSX@h | 344 PPC_STLU r1,-STKFRM(r1) 345 mflr r0 346 PPC_STL r0,STKFRM+PPC_LR_STKOFF(r1) 347 mfmsr r6 348 oris r7,r6,MSR_VSX@h |
350 cmpwi cr7,r3,0 | |
351 li r8,STKFRM-16 352 MTMSRD(r7) 353 isync | 349 li r8,STKFRM-16 350 MTMSRD(r7) 351 isync |
354 beq cr7,1f | |
355 STXVD2X(0,R1,R8) 356 bl get_vsr | 352 STXVD2X(0,R1,R8) 353 bl get_vsr |
3571: li r9,-EFAULT 3582: STXVD2X(0,R0,R4) 359 li r9,0 3603: beq cr7,4f | 354#ifdef __LITTLE_ENDIAN__ 355 XXSWAPD(0,0) 356#endif 357 STXVD2X(0,R0,R4) |
361 LXVD2X(0,R1,R8) | 358 LXVD2X(0,R1,R8) |
3624: PPC_LL r0,STKFRM+PPC_LR_STKOFF(r1) | 359 PPC_LL r0,STKFRM+PPC_LR_STKOFF(r1) |
363 mtlr r0 364 MTMSRD(r6) 365 isync 366 mr r3,r9 367 addi r1,r1,STKFRM 368 blr 369 EX_TABLE(2b,3b) | 360 mtlr r0 361 MTMSRD(r6) 362 isync 363 mr r3,r9 364 addi r1,r1,STKFRM 365 blr 366 EX_TABLE(2b,3b) |
370 | |
371#endif /* CONFIG_VSX */ 372 | 367#endif /* CONFIG_VSX */ 368 |
369/* Convert single-precision to double, without disturbing FPRs. */ 370/* conv_sp_to_dp(float *sp, double *dp) */ 371_GLOBAL(conv_sp_to_dp) 372 mfmsr r6 373 ori r7, r6, MSR_FP 374 MTMSRD(r7) 375 isync 376 stfd fr0, -16(r1) 377 lfs fr0, 0(r3) 378 stfd fr0, 0(r4) 379 lfd fr0, -16(r1) 380 MTMSRD(r6) 381 isync 382 blr 383 384/* Convert single-precision to double, without disturbing FPRs. */ 385/* conv_sp_to_dp(double *dp, float *sp) */ 386_GLOBAL(conv_dp_to_sp) 387 mfmsr r6 388 ori r7, r6, MSR_FP 389 MTMSRD(r7) 390 isync 391 stfd fr0, -16(r1) 392 lfd fr0, 0(r3) 393 stfs fr0, 0(r4) 394 lfd fr0, -16(r1) 395 MTMSRD(r6) 396 isync 397 blr 398 |
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373#endif /* CONFIG_PPC_FPU */ | 399#endif /* CONFIG_PPC_FPU */ |