mce_power.c (c1bbf387d6191e6e18f3adc4db45b922822c2ba4) mce_power.c (7b9f71f974a12740e79e918cfd58c2fce0b5b580)
1/*
2 * Machine check exception handling CPU-side for power7 and power8
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *

--- 102 unchanged lines hidden (view full) ---

111 unsigned long rs = be64_to_cpu(slb->save_area[i].vsid);
112
113 rb = (rb & ~0xFFFul) | i;
114 asm volatile("slbmte %0,%1" : : "r" (rs), "r" (rb));
115 }
116}
117#endif
118
1/*
2 * Machine check exception handling CPU-side for power7 and power8
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *

--- 102 unchanged lines hidden (view full) ---

111 unsigned long rs = be64_to_cpu(slb->save_area[i].vsid);
112
113 rb = (rb & ~0xFFFul) | i;
114 asm volatile("slbmte %0,%1" : : "r" (rs), "r" (rb));
115 }
116}
117#endif
118
119static void flush_erat(void)
120{
121 asm volatile(PPC_INVALIDATE_ERAT : : :"memory");
122}
123
124#define MCE_FLUSH_SLB 1
125#define MCE_FLUSH_TLB 2
126#define MCE_FLUSH_ERAT 3
127
128static int mce_flush(int what)
129{
130#ifdef CONFIG_PPC_STD_MMU_64
131 if (what == MCE_FLUSH_SLB) {
132 flush_and_reload_slb();
133 return 1;
134 }
135#endif
136 if (what == MCE_FLUSH_ERAT) {
137 flush_erat();
138 return 1;
139 }
140 if (what == MCE_FLUSH_TLB) {
141 if (cur_cpu_spec && cur_cpu_spec->flush_tlb) {
142 cur_cpu_spec->flush_tlb(TLB_INVAL_SCOPE_GLOBAL);
143 return 1;
144 }
145 }
146
147 return 0;
148}
149
150static int mce_handle_flush_derrors(uint64_t dsisr, uint64_t slb, uint64_t tlb, uint64_t erat)
151{
152 if ((dsisr & slb) && mce_flush(MCE_FLUSH_SLB))
153 dsisr &= ~slb;
154 if ((dsisr & erat) && mce_flush(MCE_FLUSH_ERAT))
155 dsisr &= ~erat;
156 if ((dsisr & tlb) && mce_flush(MCE_FLUSH_TLB))
157 dsisr &= ~tlb;
158 /* Any other errors we don't understand? */
159 if (dsisr)
160 return 0;
161 return 1;
162}
163
119static long mce_handle_derror(uint64_t dsisr, uint64_t slb_error_bits)
120{
121 long handled = 1;
122
123 /*
124 * flush and reload SLBs for SLB errors and flush TLBs for TLB errors.
125 * reset the error bits whenever we handle them so that at the end
126 * we can check whether we handled all of them or not.

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373
374 /* Handle UE error. */
375 if (mce_error_info.error_type == MCE_ERROR_TYPE_UE)
376 handled = mce_handle_ue_error(regs);
377
378 save_mce_event(regs, handled, &mce_error_info, nip, addr);
379 return handled;
380}
164static long mce_handle_derror(uint64_t dsisr, uint64_t slb_error_bits)
165{
166 long handled = 1;
167
168 /*
169 * flush and reload SLBs for SLB errors and flush TLBs for TLB errors.
170 * reset the error bits whenever we handle them so that at the end
171 * we can check whether we handled all of them or not.

--- 246 unchanged lines hidden (view full) ---

418
419 /* Handle UE error. */
420 if (mce_error_info.error_type == MCE_ERROR_TYPE_UE)
421 handled = mce_handle_ue_error(regs);
422
423 save_mce_event(regs, handled, &mce_error_info, nip, addr);
424 return handled;
425}
426
427static int mce_handle_derror_p9(struct pt_regs *regs)
428{
429 uint64_t dsisr = regs->dsisr;
430
431 return mce_handle_flush_derrors(dsisr,
432 P9_DSISR_MC_SLB_PARITY_MFSLB |
433 P9_DSISR_MC_SLB_MULTIHIT_MFSLB,
434
435 P9_DSISR_MC_TLB_MULTIHIT_MFTLB,
436
437 P9_DSISR_MC_ERAT_MULTIHIT);
438}
439
440static int mce_handle_ierror_p9(struct pt_regs *regs)
441{
442 uint64_t srr1 = regs->msr;
443
444 switch (P9_SRR1_MC_IFETCH(srr1)) {
445 case P9_SRR1_MC_IFETCH_SLB_PARITY:
446 case P9_SRR1_MC_IFETCH_SLB_MULTIHIT:
447 return mce_flush(MCE_FLUSH_SLB);
448 case P9_SRR1_MC_IFETCH_TLB_MULTIHIT:
449 return mce_flush(MCE_FLUSH_TLB);
450 case P9_SRR1_MC_IFETCH_ERAT_MULTIHIT:
451 return mce_flush(MCE_FLUSH_ERAT);
452 default:
453 return 0;
454 }
455}
456
457static void mce_get_derror_p9(struct pt_regs *regs,
458 struct mce_error_info *mce_err, uint64_t *addr)
459{
460 uint64_t dsisr = regs->dsisr;
461
462 mce_err->severity = MCE_SEV_ERROR_SYNC;
463 mce_err->initiator = MCE_INITIATOR_CPU;
464
465 if (dsisr & P9_DSISR_MC_USER_TLBIE)
466 *addr = regs->nip;
467 else
468 *addr = regs->dar;
469
470 if (dsisr & P9_DSISR_MC_UE) {
471 mce_err->error_type = MCE_ERROR_TYPE_UE;
472 mce_err->u.ue_error_type = MCE_UE_ERROR_LOAD_STORE;
473 } else if (dsisr & P9_DSISR_MC_UE_TABLEWALK) {
474 mce_err->error_type = MCE_ERROR_TYPE_UE;
475 mce_err->u.ue_error_type = MCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE;
476 } else if (dsisr & P9_DSISR_MC_LINK_LOAD_TIMEOUT) {
477 mce_err->error_type = MCE_ERROR_TYPE_LINK;
478 mce_err->u.link_error_type = MCE_LINK_ERROR_LOAD_TIMEOUT;
479 } else if (dsisr & P9_DSISR_MC_LINK_TABLEWALK_TIMEOUT) {
480 mce_err->error_type = MCE_ERROR_TYPE_LINK;
481 mce_err->u.link_error_type = MCE_LINK_ERROR_PAGE_TABLE_WALK_LOAD_STORE_TIMEOUT;
482 } else if (dsisr & P9_DSISR_MC_ERAT_MULTIHIT) {
483 mce_err->error_type = MCE_ERROR_TYPE_ERAT;
484 mce_err->u.erat_error_type = MCE_ERAT_ERROR_MULTIHIT;
485 } else if (dsisr & P9_DSISR_MC_TLB_MULTIHIT_MFTLB) {
486 mce_err->error_type = MCE_ERROR_TYPE_TLB;
487 mce_err->u.tlb_error_type = MCE_TLB_ERROR_MULTIHIT;
488 } else if (dsisr & P9_DSISR_MC_USER_TLBIE) {
489 mce_err->error_type = MCE_ERROR_TYPE_USER;
490 mce_err->u.user_error_type = MCE_USER_ERROR_TLBIE;
491 } else if (dsisr & P9_DSISR_MC_SLB_PARITY_MFSLB) {
492 mce_err->error_type = MCE_ERROR_TYPE_SLB;
493 mce_err->u.slb_error_type = MCE_SLB_ERROR_PARITY;
494 } else if (dsisr & P9_DSISR_MC_SLB_MULTIHIT_MFSLB) {
495 mce_err->error_type = MCE_ERROR_TYPE_SLB;
496 mce_err->u.slb_error_type = MCE_SLB_ERROR_MULTIHIT;
497 } else if (dsisr & P9_DSISR_MC_RA_LOAD) {
498 mce_err->error_type = MCE_ERROR_TYPE_RA;
499 mce_err->u.ra_error_type = MCE_RA_ERROR_LOAD;
500 } else if (dsisr & P9_DSISR_MC_RA_TABLEWALK) {
501 mce_err->error_type = MCE_ERROR_TYPE_RA;
502 mce_err->u.ra_error_type = MCE_RA_ERROR_PAGE_TABLE_WALK_LOAD_STORE;
503 } else if (dsisr & P9_DSISR_MC_RA_TABLEWALK_FOREIGN) {
504 mce_err->error_type = MCE_ERROR_TYPE_RA;
505 mce_err->u.ra_error_type = MCE_RA_ERROR_PAGE_TABLE_WALK_LOAD_STORE_FOREIGN;
506 } else if (dsisr & P9_DSISR_MC_RA_FOREIGN) {
507 mce_err->error_type = MCE_ERROR_TYPE_RA;
508 mce_err->u.ra_error_type = MCE_RA_ERROR_LOAD_STORE_FOREIGN;
509 }
510}
511
512static void mce_get_ierror_p9(struct pt_regs *regs,
513 struct mce_error_info *mce_err, uint64_t *addr)
514{
515 uint64_t srr1 = regs->msr;
516
517 switch (P9_SRR1_MC_IFETCH(srr1)) {
518 case P9_SRR1_MC_IFETCH_RA_ASYNC_STORE:
519 case P9_SRR1_MC_IFETCH_LINK_ASYNC_STORE_TIMEOUT:
520 mce_err->severity = MCE_SEV_FATAL;
521 break;
522 default:
523 mce_err->severity = MCE_SEV_ERROR_SYNC;
524 break;
525 }
526
527 mce_err->initiator = MCE_INITIATOR_CPU;
528
529 *addr = regs->nip;
530
531 switch (P9_SRR1_MC_IFETCH(srr1)) {
532 case P9_SRR1_MC_IFETCH_UE:
533 mce_err->error_type = MCE_ERROR_TYPE_UE;
534 mce_err->u.ue_error_type = MCE_UE_ERROR_IFETCH;
535 break;
536 case P9_SRR1_MC_IFETCH_SLB_PARITY:
537 mce_err->error_type = MCE_ERROR_TYPE_SLB;
538 mce_err->u.slb_error_type = MCE_SLB_ERROR_PARITY;
539 break;
540 case P9_SRR1_MC_IFETCH_SLB_MULTIHIT:
541 mce_err->error_type = MCE_ERROR_TYPE_SLB;
542 mce_err->u.slb_error_type = MCE_SLB_ERROR_MULTIHIT;
543 break;
544 case P9_SRR1_MC_IFETCH_ERAT_MULTIHIT:
545 mce_err->error_type = MCE_ERROR_TYPE_ERAT;
546 mce_err->u.erat_error_type = MCE_ERAT_ERROR_MULTIHIT;
547 break;
548 case P9_SRR1_MC_IFETCH_TLB_MULTIHIT:
549 mce_err->error_type = MCE_ERROR_TYPE_TLB;
550 mce_err->u.tlb_error_type = MCE_TLB_ERROR_MULTIHIT;
551 break;
552 case P9_SRR1_MC_IFETCH_UE_TLB_RELOAD:
553 mce_err->error_type = MCE_ERROR_TYPE_UE;
554 mce_err->u.ue_error_type = MCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH;
555 break;
556 case P9_SRR1_MC_IFETCH_LINK_TIMEOUT:
557 mce_err->error_type = MCE_ERROR_TYPE_LINK;
558 mce_err->u.link_error_type = MCE_LINK_ERROR_IFETCH_TIMEOUT;
559 break;
560 case P9_SRR1_MC_IFETCH_LINK_TABLEWALK_TIMEOUT:
561 mce_err->error_type = MCE_ERROR_TYPE_LINK;
562 mce_err->u.link_error_type = MCE_LINK_ERROR_PAGE_TABLE_WALK_IFETCH_TIMEOUT;
563 break;
564 case P9_SRR1_MC_IFETCH_RA:
565 mce_err->error_type = MCE_ERROR_TYPE_RA;
566 mce_err->u.ra_error_type = MCE_RA_ERROR_IFETCH;
567 break;
568 case P9_SRR1_MC_IFETCH_RA_TABLEWALK:
569 mce_err->error_type = MCE_ERROR_TYPE_RA;
570 mce_err->u.ra_error_type = MCE_RA_ERROR_PAGE_TABLE_WALK_IFETCH;
571 break;
572 case P9_SRR1_MC_IFETCH_RA_ASYNC_STORE:
573 mce_err->error_type = MCE_ERROR_TYPE_RA;
574 mce_err->u.ra_error_type = MCE_RA_ERROR_STORE;
575 break;
576 case P9_SRR1_MC_IFETCH_LINK_ASYNC_STORE_TIMEOUT:
577 mce_err->error_type = MCE_ERROR_TYPE_LINK;
578 mce_err->u.link_error_type = MCE_LINK_ERROR_STORE_TIMEOUT;
579 break;
580 case P9_SRR1_MC_IFETCH_RA_TABLEWALK_FOREIGN:
581 mce_err->error_type = MCE_ERROR_TYPE_RA;
582 mce_err->u.ra_error_type = MCE_RA_ERROR_PAGE_TABLE_WALK_IFETCH_FOREIGN;
583 break;
584 default:
585 break;
586 }
587}
588
589long __machine_check_early_realmode_p9(struct pt_regs *regs)
590{
591 uint64_t nip, addr;
592 long handled;
593 struct mce_error_info mce_error_info = { 0 };
594
595 nip = regs->nip;
596
597 if (P9_SRR1_MC_LOADSTORE(regs->msr)) {
598 handled = mce_handle_derror_p9(regs);
599 mce_get_derror_p9(regs, &mce_error_info, &addr);
600 } else {
601 handled = mce_handle_ierror_p9(regs);
602 mce_get_ierror_p9(regs, &mce_error_info, &addr);
603 }
604
605 /* Handle UE error. */
606 if (mce_error_info.error_type == MCE_ERROR_TYPE_UE)
607 handled = mce_handle_ue_error(regs);
608
609 save_mce_event(regs, handled, &mce_error_info, nip, addr);
610 return handled;
611}