| head_8xx.S (14e77332e74603efab8347c89d3cda447c3b97c9) | head_8xx.S (2da37761671b5bdedbe04e6469cfa57cd6b6ae45) |
|---|---|
| 1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * PowerPC version 4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 5 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP 6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 7 * Low-level exception handlers and MMU support 8 * rewritten by Paul Mackerras. --- 4 unchanged lines hidden (view full) --- 13 * This file contains low-level support and setup for PowerPC 8xx 14 * embedded processors, including trap and interrupt dispatch. 15 */ 16 17#include <linux/init.h> 18#include <linux/magic.h> 19#include <linux/pgtable.h> 20#include <linux/sizes.h> | 1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * PowerPC version 4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 5 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP 6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 7 * Low-level exception handlers and MMU support 8 * rewritten by Paul Mackerras. --- 4 unchanged lines hidden (view full) --- 13 * This file contains low-level support and setup for PowerPC 8xx 14 * embedded processors, including trap and interrupt dispatch. 15 */ 16 17#include <linux/init.h> 18#include <linux/magic.h> 19#include <linux/pgtable.h> 20#include <linux/sizes.h> |
| 21#include <linux/linkage.h> 22 |
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| 21#include <asm/processor.h> 22#include <asm/page.h> 23#include <asm/mmu.h> 24#include <asm/cache.h> 25#include <asm/cputable.h> 26#include <asm/thread_info.h> 27#include <asm/ppc_asm.h> 28#include <asm/asm-offsets.h> --- 591 unchanged lines hidden (view full) --- 620/* Set up the initial MMU state so we can do the first level of 621 * kernel initialization. This maps the first 8 MBytes of memory 1:1 622 * virtual to physical. Also, set the cache mode since that is defined 623 * by TLB entries and perform any additional mapping (like of the IMMR). 624 * If configured to pin some TLBs, we pin the first 8 Mbytes of kernel, 625 * 24 Mbytes of data, and the 512k IMMR space. Anything not covered by 626 * these mappings is mapped by page tables. 627 */ | 23#include <asm/processor.h> 24#include <asm/page.h> 25#include <asm/mmu.h> 26#include <asm/cache.h> 27#include <asm/cputable.h> 28#include <asm/thread_info.h> 29#include <asm/ppc_asm.h> 30#include <asm/asm-offsets.h> --- 591 unchanged lines hidden (view full) --- 622/* Set up the initial MMU state so we can do the first level of 623 * kernel initialization. This maps the first 8 MBytes of memory 1:1 624 * virtual to physical. Also, set the cache mode since that is defined 625 * by TLB entries and perform any additional mapping (like of the IMMR). 626 * If configured to pin some TLBs, we pin the first 8 Mbytes of kernel, 627 * 24 Mbytes of data, and the 512k IMMR space. Anything not covered by 628 * these mappings is mapped by page tables. 629 */ |
| 628initial_mmu: | 630SYM_FUNC_START_LOCAL(initial_mmu) |
| 629 li r8, 0 630 mtspr SPRN_MI_CTR, r8 /* remove PINNED ITLB entries */ 631 lis r10, MD_TWAM@h 632 mtspr SPRN_MD_CTR, r10 /* remove PINNED DTLB entries */ 633 634 tlbia /* Invalidate all TLB entries */ 635 636 lis r8, MI_APG_INIT@h /* Set protection modes */ --- 44 unchanged lines hidden (view full) --- 681 mfspr r8, SPRN_DER 682#ifdef CONFIG_PERF_EVENTS 683 rlwinm r8, r8, 0, ~0xc 684#else 685 rlwinm r8, r8, 0, ~0x8 686#endif 687 mtspr SPRN_DER, r8 688 blr | 631 li r8, 0 632 mtspr SPRN_MI_CTR, r8 /* remove PINNED ITLB entries */ 633 lis r10, MD_TWAM@h 634 mtspr SPRN_MD_CTR, r10 /* remove PINNED DTLB entries */ 635 636 tlbia /* Invalidate all TLB entries */ 637 638 lis r8, MI_APG_INIT@h /* Set protection modes */ --- 44 unchanged lines hidden (view full) --- 683 mfspr r8, SPRN_DER 684#ifdef CONFIG_PERF_EVENTS 685 rlwinm r8, r8, 0, ~0xc 686#else 687 rlwinm r8, r8, 0, ~0x8 688#endif 689 mtspr SPRN_DER, r8 690 blr |
| 691SYM_FUNC_END(initial_mmu) |
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| 689 690_GLOBAL(mmu_pin_tlb) 691 lis r9, (1f - PAGE_OFFSET)@h 692 ori r9, r9, (1f - PAGE_OFFSET)@l 693 mfmsr r10 694 mflr r11 695 li r12, MSR_KERNEL & ~(MSR_IR | MSR_DR | MSR_RI) 696 rlwinm r0, r10, 0, ~MSR_RI --- 93 unchanged lines hidden --- | 692 693_GLOBAL(mmu_pin_tlb) 694 lis r9, (1f - PAGE_OFFSET)@h 695 ori r9, r9, (1f - PAGE_OFFSET)@l 696 mfmsr r10 697 mflr r11 698 li r12, MSR_KERNEL & ~(MSR_IR | MSR_DR | MSR_RI) 699 rlwinm r0, r10, 0, ~MSR_RI --- 93 unchanged lines hidden --- |