head_44x.S (e7f75ad01d590243904c2d95ab47e6b2e9ef6dad) head_44x.S (b4e8c8dd8456c1d3685fb5b715c9795d250f500e)
1/*
2 * Kernel execution entry point code.
3 *
4 * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
5 * Initial PowerPC version.
6 * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
7 * Rewritten for PReP
8 * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>

--- 701 unchanged lines hidden (view full) ---

710_GLOBAL(init_cpu_state)
711 mflr r22
712#ifdef CONFIG_PPC_47x
713 /* We use the PVR to differenciate 44x cores from 476 */
714 mfspr r3,SPRN_PVR
715 srwi r3,r3,16
716 cmplwi cr0,r3,PVR_476@h
717 beq head_start_47x
1/*
2 * Kernel execution entry point code.
3 *
4 * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
5 * Initial PowerPC version.
6 * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
7 * Rewritten for PReP
8 * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>

--- 701 unchanged lines hidden (view full) ---

710_GLOBAL(init_cpu_state)
711 mflr r22
712#ifdef CONFIG_PPC_47x
713 /* We use the PVR to differenciate 44x cores from 476 */
714 mfspr r3,SPRN_PVR
715 srwi r3,r3,16
716 cmplwi cr0,r3,PVR_476@h
717 beq head_start_47x
718 cmplwi cr0,r3,PVR_476_ISS@h
719 beq head_start_47x
718#endif /* CONFIG_PPC_47x */
719
720/*
721 * In case the firmware didn't do it, we apply some workarounds
722 * that are good for all 440 core variants here
723 */
724 mfspr r3,SPRN_CCR0
725 rlwinm r3,r3,0,0,27 /* disable icache prefetch */

--- 430 unchanged lines hidden --- 		720#endif /* CONFIG_PPC_47x */
721
722/*
723 * In case the firmware didn't do it, we apply some workarounds
724 * that are good for all 440 core variants here
725 */
726 mfspr r3,SPRN_CCR0
727 rlwinm r3,r3,0,0,27 /* disable icache prefetch */

--- 430 unchanged lines hidden ---