exceptions-64e.S (ba67cf5cf2ce10ad86a212b70f8c7c75d93a5016) exceptions-64e.S (a1d0d98daf6ce580d017a43b09fe30a375cde3e8)
1/*
2 * Boot code and exception vectors for Book3E processors
3 *
4 * Copyright (C) 2007 Ben. Herrenschmidt (benh@kernel.crashing.org), IBM Corp.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version

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859 blr
860
861have_hes:
862 /* Setup MAS 0,1,2,3 and 7 for tlbwe of a 1G entry that maps the
863 * kernel linear mapping. We also set MAS8 once for all here though
864 * that will have to be made dependent on whether we are running under
865 * a hypervisor I suppose.
866 */
1/*
2 * Boot code and exception vectors for Book3E processors
3 *
4 * Copyright (C) 2007 Ben. Herrenschmidt (benh@kernel.crashing.org), IBM Corp.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version

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859 blr
860
861have_hes:
862 /* Setup MAS 0,1,2,3 and 7 for tlbwe of a 1G entry that maps the
863 * kernel linear mapping. We also set MAS8 once for all here though
864 * that will have to be made dependent on whether we are running under
865 * a hypervisor I suppose.
866 */
867 ori r3,r3,MAS0_HES | MAS0_WQ_ALLWAYS
868 mtspr SPRN_MAS0,r3
867
868 /* BEWARE, MAGIC
869 * This code is called as an ordinary function on the boot CPU. But to
870 * avoid duplication, this code is also used in SCOM bringup of
871 * secondary CPUs. We read the code between the initial_tlb_code_start
872 * and initial_tlb_code_end labels one instruction at a time and RAM it
873 * into the new core via SCOM. That doesn't process branches, so there
874 * must be none between those two labels. It also means if this code
875 * ever takes any parameters, the SCOM code must also be updated to
876 * provide them.
877 */
878 .globl a2_tlbinit_code_start
879a2_tlbinit_code_start:
880
881 ori r11,r3,MAS0_WQ_ALLWAYS
882 oris r11,r11,MAS0_ESEL(3)@h /* Use way 3: workaround A2 erratum 376 */
883 mtspr SPRN_MAS0,r11
869 lis r3,(MAS1_VALID | MAS1_IPROT)@h
870 ori r3,r3,BOOK3E_PAGESZ_1GB << MAS1_TSIZE_SHIFT
871 mtspr SPRN_MAS1,r3
872 LOAD_REG_IMMEDIATE(r3, PAGE_OFFSET | MAS2_M)
873 mtspr SPRN_MAS2,r3
874 li r3,MAS3_SR | MAS3_SW | MAS3_SX
875 mtspr SPRN_MAS7_MAS3,r3
876 li r3,0
877 mtspr SPRN_MAS8,r3
878
879 /* Write the TLB entry */
880 tlbwe
881
884 lis r3,(MAS1_VALID | MAS1_IPROT)@h
885 ori r3,r3,BOOK3E_PAGESZ_1GB << MAS1_TSIZE_SHIFT
886 mtspr SPRN_MAS1,r3
887 LOAD_REG_IMMEDIATE(r3, PAGE_OFFSET | MAS2_M)
888 mtspr SPRN_MAS2,r3
889 li r3,MAS3_SR | MAS3_SW | MAS3_SX
890 mtspr SPRN_MAS7_MAS3,r3
891 li r3,0
892 mtspr SPRN_MAS8,r3
893
894 /* Write the TLB entry */
895 tlbwe
896
897 .globl a2_tlbinit_after_linear_map
898a2_tlbinit_after_linear_map:
899
882 /* Now we branch the new virtual address mapped by this entry */
883 LOAD_REG_IMMEDIATE(r3,1f)
884 mtctr r3
885 bctr
886
8871: /* We are now running at PAGE_OFFSET, clean the TLB of everything
900 /* Now we branch the new virtual address mapped by this entry */
901 LOAD_REG_IMMEDIATE(r3,1f)
902 mtctr r3
903 bctr
904
9051: /* We are now running at PAGE_OFFSET, clean the TLB of everything
888 * else (XXX we should scan for bolted crap from the firmware too)
906 * else (including IPROTed things left by firmware)
907 * r4 = TLBnCFG
908 * r3 = current address (more or less)
889 */
909 */
910
911 li r5,0
912 mtspr SPRN_MAS6,r5
913 tlbsx 0,r3
914
915 rlwinm r9,r4,0,TLBnCFG_N_ENTRY
916 rlwinm r10,r4,8,0xff
917 addi r10,r10,-1 /* Get inner loop mask */
918
919 li r3,1
920
921 mfspr r5,SPRN_MAS1
922 rlwinm r5,r5,0,(~(MAS1_VALID|MAS1_IPROT))
923
924 mfspr r6,SPRN_MAS2
925 rldicr r6,r6,0,51 /* Extract EPN */
926
927 mfspr r7,SPRN_MAS0
928 rlwinm r7,r7,0,0xffff0fff /* Clear HES and WQ */
929
930 rlwinm r8,r7,16,0xfff /* Extract ESEL */
931
9322: add r4,r3,r8
933 and r4,r4,r10
934
935 rlwimi r7,r4,16,MAS0_ESEL_MASK
936
937 mtspr SPRN_MAS0,r7
938 mtspr SPRN_MAS1,r5
939 mtspr SPRN_MAS2,r6
940 tlbwe
941
942 addi r3,r3,1
943 and. r4,r3,r10
944
945 bne 3f
946 addis r6,r6,(1<<30)@h
9473:
948 cmpw r3,r9
949 blt 2b
950
951 .globl a2_tlbinit_after_iprot_flush
952a2_tlbinit_after_iprot_flush:
953
890 PPC_TLBILX(0,0,0)
891 sync
892 isync
893
954 PPC_TLBILX(0,0,0)
955 sync
956 isync
957
958 .globl a2_tlbinit_code_end
959a2_tlbinit_code_end:
960
894 /* We translate LR and return */
895 mflr r3
896 tovirt(r3,r3)
897 mtlr r3
898 blr
899
900/*
901 * Main entry (boot CPU, thread 0)

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961 /* We translate LR and return */
962 mflr r3
963 tovirt(r3,r3)
964 mtlr r3
965 blr
966
967/*
968 * Main entry (boot CPU, thread 0)

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