entry_32.S (de4fb176622d54a82ea3ceb7362392aaf5ff0b5a) entry_32.S (838ee286ecc9a3c76e6bd8f5aaad0c8c5c66b9ca)
1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * PowerPC version
4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
5 * Rewritten by Cort Dougan (cort@fsmlabs.com) for PReP
6 * Copyright (C) 1996 Cort Dougan <cort@fsmlabs.com>
7 * Adapted for Power Macintosh by Paul Mackerras.
8 * Low-level exception handlers and MMU support

--- 541 unchanged lines hidden (view full) ---

550 RESTORE_xSRR(SRR0,SRR1);
551 RESTORE_xSRR(CSRR0,CSRR1);
552 RESTORE_xSRR(DSRR0,DSRR1);
553 RESTORE_MMU_REGS;
554 RET_FROM_EXC_LEVEL(SPRN_MCSRR0, SPRN_MCSRR1, PPC_RFMCI)
555_ASM_NOKPROBE_SYMBOL(ret_from_mcheck_exc)
556#endif /* CONFIG_BOOKE */
557#endif /* !(CONFIG_4xx || CONFIG_BOOKE) */
1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * PowerPC version
4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
5 * Rewritten by Cort Dougan (cort@fsmlabs.com) for PReP
6 * Copyright (C) 1996 Cort Dougan <cort@fsmlabs.com>
7 * Adapted for Power Macintosh by Paul Mackerras.
8 * Low-level exception handlers and MMU support

--- 541 unchanged lines hidden (view full) ---

550 RESTORE_xSRR(SRR0,SRR1);
551 RESTORE_xSRR(CSRR0,CSRR1);
552 RESTORE_xSRR(DSRR0,DSRR1);
553 RESTORE_MMU_REGS;
554 RET_FROM_EXC_LEVEL(SPRN_MCSRR0, SPRN_MCSRR1, PPC_RFMCI)
555_ASM_NOKPROBE_SYMBOL(ret_from_mcheck_exc)
556#endif /* CONFIG_BOOKE */
557#endif /* !(CONFIG_4xx || CONFIG_BOOKE) */
558
559/*
560 * PROM code for specific machines follows. Put it
561 * here so it's easy to add arch-specific sections later.
562 * -- Cort
563 */
564#ifdef CONFIG_PPC_RTAS
565/*
566 * On CHRP, the Run-Time Abstraction Services (RTAS) have to be
567 * called with the MMU off.
568 */
569_GLOBAL(enter_rtas)
570 stwu r1,-INT_FRAME_SIZE(r1)
571 mflr r0
572 stw r0,INT_FRAME_SIZE+4(r1)
573 LOAD_REG_ADDR(r4, rtas)
574 lis r6,1f@ha /* physical return address for rtas */
575 addi r6,r6,1f@l
576 tophys(r6,r6)
577 lwz r8,RTASENTRY(r4)
578 lwz r4,RTASBASE(r4)
579 mfmsr r9
580 stw r9,8(r1)
581 LOAD_REG_IMMEDIATE(r0,MSR_KERNEL)
582 mtmsr r0 /* disable interrupts so SRR0/1 don't get trashed */
583 li r9,MSR_KERNEL & ~(MSR_IR|MSR_DR)
584 mtlr r6
585 stw r1, THREAD + RTAS_SP(r2)
586 mtspr SPRN_SRR0,r8
587 mtspr SPRN_SRR1,r9
588 rfi
5891:
590 lis r8, 1f@h
591 ori r8, r8, 1f@l
592 LOAD_REG_IMMEDIATE(r9,MSR_KERNEL)
593 mtspr SPRN_SRR0,r8
594 mtspr SPRN_SRR1,r9
595 rfi /* Reactivate MMU translation */
5961:
597 lwz r8,INT_FRAME_SIZE+4(r1) /* get return address */
598 lwz r9,8(r1) /* original msr value */
599 addi r1,r1,INT_FRAME_SIZE
600 li r0,0
601 stw r0, THREAD + RTAS_SP(r2)
602 mtlr r8
603 mtmsr r9
604 blr /* return to caller */
605_ASM_NOKPROBE_SYMBOL(enter_rtas)
606#endif /* CONFIG_PPC_RTAS */