sstep.h (e5451c8f8330e03ad3cfa16048b4daf961af434f) sstep.h (3cdfcbfd32b9d1c0d4a6fa80ee9c390927aab948)
1/*
2 * Copyright (C) 2004 Paul Mackerras <paulus@au.ibm.com>, IBM
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */

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18 * These macros tell us if an instruction is a mtmsrd or rfid.
19 * Note that IS_MTMSRD returns true for both an mtmsr (32-bit)
20 * and an mtmsrd (64-bit).
21 */
22#define IS_MTMSRD(instr) (((instr) & 0xfc0007be) == 0x7c000124)
23#define IS_RFID(instr) (((instr) & 0xfc0007fe) == 0x4c000024)
24#define IS_RFI(instr) (((instr) & 0xfc0007fe) == 0x4c000064)
25
1/*
2 * Copyright (C) 2004 Paul Mackerras <paulus@au.ibm.com>, IBM
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */

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18 * These macros tell us if an instruction is a mtmsrd or rfid.
19 * Note that IS_MTMSRD returns true for both an mtmsr (32-bit)
20 * and an mtmsrd (64-bit).
21 */
22#define IS_MTMSRD(instr) (((instr) & 0xfc0007be) == 0x7c000124)
23#define IS_RFID(instr) (((instr) & 0xfc0007fe) == 0x4c000024)
24#define IS_RFI(instr) (((instr) & 0xfc0007fe) == 0x4c000064)
25
26/* Emulate instructions that cause a transfer of control. */
27extern int emulate_step(struct pt_regs *regs, unsigned int instr);
28
29enum instruction_type {
30 COMPUTE, /* arith/logical/CR op, etc. */
31 LOAD,
32 LOAD_MULTI,
33 LOAD_FP,
34 LOAD_VMX,
35 LOAD_VSX,
36 STORE,

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50 MTMSR,
51 RFI,
52 INTERRUPT,
53 UNKNOWN
54};
55
56#define INSTR_TYPE_MASK 0x1f
57
26enum instruction_type {
27 COMPUTE, /* arith/logical/CR op, etc. */
28 LOAD,
29 LOAD_MULTI,
30 LOAD_FP,
31 LOAD_VMX,
32 LOAD_VSX,
33 STORE,

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47 MTMSR,
48 RFI,
49 INTERRUPT,
50 UNKNOWN
51};
52
53#define INSTR_TYPE_MASK 0x1f
54
55/* Compute flags, ORed in with type */
56#define SETREG 0x20
57#define SETCC 0x40
58#define SETXER 0x80
59
60/* Branch flags, ORed in with type */
61#define SETLK 0x20
62#define BRTAKEN 0x40
63#define DECCTR 0x80
64
58/* Load/store flags, ORed in with type */
59#define SIGNEXT 0x20
60#define UPDATE 0x40 /* matches bit in opcode 31 instructions */
61#define BYTEREV 0x80
62
65/* Load/store flags, ORed in with type */
66#define SIGNEXT 0x20
67#define UPDATE 0x40 /* matches bit in opcode 31 instructions */
68#define BYTEREV 0x80
69
70/* Barrier type field, ORed in with type */
71#define BARRIER_MASK 0xe0
72#define BARRIER_SYNC 0x00
73#define BARRIER_ISYNC 0x20
74#define BARRIER_EIEIO 0x40
75#define BARRIER_LWSYNC 0x60
76#define BARRIER_PTESYNC 0x80
77
63/* Cacheop values, ORed in with type */
64#define CACHEOP_MASK 0x700
65#define DCBST 0
66#define DCBF 0x100
67#define DCBTST 0x200
68#define DCBT 0x300
69#define ICBI 0x400
70

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78 int type;
79 int reg;
80 unsigned long val;
81 /* For LOAD/STORE/LARX/STCX */
82 unsigned long ea;
83 int update_reg;
84 /* For MFSPR */
85 int spr;
78/* Cacheop values, ORed in with type */
79#define CACHEOP_MASK 0x700
80#define DCBST 0
81#define DCBF 0x100
82#define DCBTST 0x200
83#define DCBT 0x300
84#define ICBI 0x400
85

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93 int type;
94 int reg;
95 unsigned long val;
96 /* For LOAD/STORE/LARX/STCX */
97 unsigned long ea;
98 int update_reg;
99 /* For MFSPR */
100 int spr;
101 u32 ccval;
102 u32 xerval;
86};
87
103};
104
88extern int analyse_instr(struct instruction_op *op, struct pt_regs *regs,
105/*
106 * Decode an instruction, and return information about it in *op
107 * without changing *regs.
108 *
109 * Return value is 1 if the instruction can be emulated just by
110 * updating *regs with the information in *op, -1 if we need the
111 * GPRs but *regs doesn't contain the full register set, or 0
112 * otherwise.
113 */
114extern int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
89 unsigned int instr);
115 unsigned int instr);
116
117/*
118 * Emulate an instruction that can be executed just by updating
119 * fields in *regs.
120 */
121void emulate_update_regs(struct pt_regs *reg, struct instruction_op *op);
122
123/*
124 * Emulate instructions that cause a transfer of control,
125 * arithmetic/logical instructions, loads and stores,
126 * cache operations and barriers.
127 *
128 * Returns 1 if the instruction was emulated successfully,
129 * 0 if it could not be emulated, or -1 for an instruction that
130 * should not be emulated (rfid, mtmsrd clearing MSR_RI, etc.).
131 */
132extern int emulate_step(struct pt_regs *regs, unsigned int instr);
133