| reg.h (692d96552c9a86a919fe6b5b82288a6c77c015a5) | reg.h (b3d627a5f2bf1a9a486f65af6f7c2ce0e09b3d12) |
|---|---|
| 1/* 2 * Contains the definition of registers common to all PowerPC variants. 3 * If a register definition has been changed in a different PowerPC 4 * variant, we will case it in #ifndef XXX ... #endif, and have the 5 * number used in the Programming Environments Manual For 32-Bit 6 * Implementations of the PowerPC Architecture (a.k.a. Green Book) here. 7 */ 8 --- 257 unchanged lines hidden (view full) --- 266#define SPRN_HDEC 0x136 /* Hypervisor Decrementer */ 267#define SPRN_HIOR 0x137 /* 970 Hypervisor interrupt offset */ 268#define SPRN_RMOR 0x138 /* Real mode offset register */ 269#define SPRN_HRMOR 0x139 /* Real mode offset register */ 270#define SPRN_HSRR0 0x13A /* Hypervisor Save/Restore 0 */ 271#define SPRN_HSRR1 0x13B /* Hypervisor Save/Restore 1 */ 272#define SPRN_IC 0x350 /* Virtual Instruction Count */ 273#define SPRN_VTB 0x351 /* Virtual Time Base */ | 1/* 2 * Contains the definition of registers common to all PowerPC variants. 3 * If a register definition has been changed in a different PowerPC 4 * variant, we will case it in #ifndef XXX ... #endif, and have the 5 * number used in the Programming Environments Manual For 32-Bit 6 * Implementations of the PowerPC Architecture (a.k.a. Green Book) here. 7 */ 8 --- 257 unchanged lines hidden (view full) --- 266#define SPRN_HDEC 0x136 /* Hypervisor Decrementer */ 267#define SPRN_HIOR 0x137 /* 970 Hypervisor interrupt offset */ 268#define SPRN_RMOR 0x138 /* Real mode offset register */ 269#define SPRN_HRMOR 0x139 /* Real mode offset register */ 270#define SPRN_HSRR0 0x13A /* Hypervisor Save/Restore 0 */ 271#define SPRN_HSRR1 0x13B /* Hypervisor Save/Restore 1 */ 272#define SPRN_IC 0x350 /* Virtual Instruction Count */ 273#define SPRN_VTB 0x351 /* Virtual Time Base */ |
| 274#define SPRN_PMICR 0x354 /* Power Management Idle Control Reg */ 275#define SPRN_PMSR 0x355 /* Power Management Status Reg */ 276#define SPRN_PMCR 0x374 /* Power Management Control Register */ 277 |
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| 274/* HFSCR and FSCR bit numbers are the same */ 275#define FSCR_TAR_LG 8 /* Enable Target Address Register */ 276#define FSCR_EBB_LG 7 /* Enable Event Based Branching */ 277#define FSCR_TM_LG 5 /* Enable Transactional Memory */ 278#define FSCR_BHRB_LG 4 /* Enable Branch History Rolling Buffer*/ 279#define FSCR_PM_LG 3 /* Enable prob/priv access to PMU SPRs */ 280#define FSCR_DSCR_LG 2 /* Enable Data Stream Control Register */ 281#define FSCR_VECVSX_LG 1 /* Enable VMX/VSX */ --- 290 unchanged lines hidden (view full) --- 572#define SPRN_ASR 0x118 /* Address Space Register */ 573#define SPRN_SIA 0x3BB /* Sampled Instruction Address Register */ 574#define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */ 575#define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */ 576#define SPRN_SPRG2 0x112 /* Special Purpose Register General 2 */ 577#define SPRN_SPRG3 0x113 /* Special Purpose Register General 3 */ 578#define SPRN_USPRG3 0x103 /* SPRG3 userspace read */ 579#define SPRN_SPRG4 0x114 /* Special Purpose Register General 4 */ | 278/* HFSCR and FSCR bit numbers are the same */ 279#define FSCR_TAR_LG 8 /* Enable Target Address Register */ 280#define FSCR_EBB_LG 7 /* Enable Event Based Branching */ 281#define FSCR_TM_LG 5 /* Enable Transactional Memory */ 282#define FSCR_BHRB_LG 4 /* Enable Branch History Rolling Buffer*/ 283#define FSCR_PM_LG 3 /* Enable prob/priv access to PMU SPRs */ 284#define FSCR_DSCR_LG 2 /* Enable Data Stream Control Register */ 285#define FSCR_VECVSX_LG 1 /* Enable VMX/VSX */ --- 290 unchanged lines hidden (view full) --- 576#define SPRN_ASR 0x118 /* Address Space Register */ 577#define SPRN_SIA 0x3BB /* Sampled Instruction Address Register */ 578#define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */ 579#define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */ 580#define SPRN_SPRG2 0x112 /* Special Purpose Register General 2 */ 581#define SPRN_SPRG3 0x113 /* Special Purpose Register General 3 */ 582#define SPRN_USPRG3 0x103 /* SPRG3 userspace read */ 583#define SPRN_SPRG4 0x114 /* Special Purpose Register General 4 */ |
| 584#define SPRN_USPRG4 0x104 /* SPRG4 userspace read */ |
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| 580#define SPRN_SPRG5 0x115 /* Special Purpose Register General 5 */ | 585#define SPRN_SPRG5 0x115 /* Special Purpose Register General 5 */ |
| 586#define SPRN_USPRG5 0x105 /* SPRG5 userspace read */ |
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| 581#define SPRN_SPRG6 0x116 /* Special Purpose Register General 6 */ | 587#define SPRN_SPRG6 0x116 /* Special Purpose Register General 6 */ |
| 588#define SPRN_USPRG6 0x106 /* SPRG6 userspace read */ |
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| 582#define SPRN_SPRG7 0x117 /* Special Purpose Register General 7 */ | 589#define SPRN_SPRG7 0x117 /* Special Purpose Register General 7 */ |
| 590#define SPRN_USPRG7 0x107 /* SPRG7 userspace read */ |
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| 583#define SPRN_SRR0 0x01A /* Save/Restore Register 0 */ 584#define SPRN_SRR1 0x01B /* Save/Restore Register 1 */ 585#define SRR1_ISI_NOPT 0x40000000 /* ISI: Not found in hash */ 586#define SRR1_ISI_N_OR_G 0x10000000 /* ISI: Access is no-exec or G */ 587#define SRR1_ISI_PROT 0x08000000 /* ISI: Other protection fault */ 588#define SRR1_WAKEMASK 0x00380000 /* reason for wakeup */ 589#define SRR1_WAKESYSERR 0x00300000 /* System error */ 590#define SRR1_WAKEEE 0x00200000 /* External interrupt */ --- 68 unchanged lines hidden (view full) --- 659#define MMCR0_KERNEL_DISABLE MMCR0_FCS 660#define MMCR0_FCP 0x20000000UL /* freeze in problem state */ 661#define MMCR0_PROBLEM_DISABLE MMCR0_FCP 662#define MMCR0_FCM1 0x10000000UL /* freeze counters while MSR mark = 1 */ 663#define MMCR0_FCM0 0x08000000UL /* freeze counters while MSR mark = 0 */ 664#define MMCR0_PMXE 0x04000000UL /* performance monitor exception enable */ 665#define MMCR0_FCECE 0x02000000UL /* freeze ctrs on enabled cond or event */ 666#define MMCR0_TBEE 0x00400000UL /* time base exception enable */ | 591#define SPRN_SRR0 0x01A /* Save/Restore Register 0 */ 592#define SPRN_SRR1 0x01B /* Save/Restore Register 1 */ 593#define SRR1_ISI_NOPT 0x40000000 /* ISI: Not found in hash */ 594#define SRR1_ISI_N_OR_G 0x10000000 /* ISI: Access is no-exec or G */ 595#define SRR1_ISI_PROT 0x08000000 /* ISI: Other protection fault */ 596#define SRR1_WAKEMASK 0x00380000 /* reason for wakeup */ 597#define SRR1_WAKESYSERR 0x00300000 /* System error */ 598#define SRR1_WAKEEE 0x00200000 /* External interrupt */ --- 68 unchanged lines hidden (view full) --- 667#define MMCR0_KERNEL_DISABLE MMCR0_FCS 668#define MMCR0_FCP 0x20000000UL /* freeze in problem state */ 669#define MMCR0_PROBLEM_DISABLE MMCR0_FCP 670#define MMCR0_FCM1 0x10000000UL /* freeze counters while MSR mark = 1 */ 671#define MMCR0_FCM0 0x08000000UL /* freeze counters while MSR mark = 0 */ 672#define MMCR0_PMXE 0x04000000UL /* performance monitor exception enable */ 673#define MMCR0_FCECE 0x02000000UL /* freeze ctrs on enabled cond or event */ 674#define MMCR0_TBEE 0x00400000UL /* time base exception enable */ |
| 675#define MMCR0_BHRBA 0x00200000UL /* BHRB Access allowed in userspace */ |
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| 667#define MMCR0_EBE 0x00100000UL /* Event based branch enable */ 668#define MMCR0_PMCC 0x000c0000UL /* PMC control */ 669#define MMCR0_PMCC_U6 0x00080000UL /* PMC1-6 are R/W by user (PR) */ 670#define MMCR0_PMC1CE 0x00008000UL /* PMC1 count enable*/ 671#define MMCR0_PMCjCE 0x00004000UL /* PMCj count enable*/ 672#define MMCR0_TRIGGER 0x00002000UL /* TRIGGER enable */ | 676#define MMCR0_EBE 0x00100000UL /* Event based branch enable */ 677#define MMCR0_PMCC 0x000c0000UL /* PMC control */ 678#define MMCR0_PMCC_U6 0x00080000UL /* PMC1-6 are R/W by user (PR) */ 679#define MMCR0_PMC1CE 0x00008000UL /* PMC1 count enable*/ 680#define MMCR0_PMCjCE 0x00004000UL /* PMCj count enable*/ 681#define MMCR0_TRIGGER 0x00002000UL /* TRIGGER enable */ |
| 682#define MMCR0_PMAO_SYNC 0x00000800UL /* PMU interrupt is synchronous */ |
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| 673#define MMCR0_PMAO 0x00000080UL /* performance monitor alert has occurred, set to 0 after handling exception */ 674#define MMCR0_SHRFC 0x00000040UL /* SHRre freeze conditions between threads */ 675#define MMCR0_FC56 0x00000010UL /* freeze counters 5 and 6 */ 676#define MMCR0_FCTI 0x00000008UL /* freeze counters in tags inactive mode */ 677#define MMCR0_FCTA 0x00000004UL /* freeze counters in tags active mode */ 678#define MMCR0_FCWAIT 0x00000002UL /* freeze counter in WAIT state */ 679#define MMCR0_FCHV 0x00000001UL /* freeze conditions in hypervisor mode */ 680#define SPRN_MMCR1 798 --- 17 unchanged lines hidden (view full) --- 698#define POWER7P_MMCRA_SDAR_VALID 0x08000000 /* P7+ SDAR contents valid */ 699 700#define SPRN_MMCRH 316 /* Hypervisor monitor mode control register */ 701#define SPRN_MMCRS 894 /* Supervisor monitor mode control register */ 702#define SPRN_MMCRC 851 /* Core monitor mode control register */ 703#define SPRN_EBBHR 804 /* Event based branch handler register */ 704#define SPRN_EBBRR 805 /* Event based branch return register */ 705#define SPRN_BESCR 806 /* Branch event status and control register */ | 683#define MMCR0_PMAO 0x00000080UL /* performance monitor alert has occurred, set to 0 after handling exception */ 684#define MMCR0_SHRFC 0x00000040UL /* SHRre freeze conditions between threads */ 685#define MMCR0_FC56 0x00000010UL /* freeze counters 5 and 6 */ 686#define MMCR0_FCTI 0x00000008UL /* freeze counters in tags inactive mode */ 687#define MMCR0_FCTA 0x00000004UL /* freeze counters in tags active mode */ 688#define MMCR0_FCWAIT 0x00000002UL /* freeze counter in WAIT state */ 689#define MMCR0_FCHV 0x00000001UL /* freeze conditions in hypervisor mode */ 690#define SPRN_MMCR1 798 --- 17 unchanged lines hidden (view full) --- 708#define POWER7P_MMCRA_SDAR_VALID 0x08000000 /* P7+ SDAR contents valid */ 709 710#define SPRN_MMCRH 316 /* Hypervisor monitor mode control register */ 711#define SPRN_MMCRS 894 /* Supervisor monitor mode control register */ 712#define SPRN_MMCRC 851 /* Core monitor mode control register */ 713#define SPRN_EBBHR 804 /* Event based branch handler register */ 714#define SPRN_EBBRR 805 /* Event based branch return register */ 715#define SPRN_BESCR 806 /* Branch event status and control register */ |
| 716#define BESCR_GE 0x8000000000000000ULL /* Global Enable */ |
|
| 706#define SPRN_WORT 895 /* Workload optimization register - thread */ 707 708#define SPRN_PMC1 787 709#define SPRN_PMC2 788 710#define SPRN_PMC3 789 711#define SPRN_PMC4 790 712#define SPRN_PMC5 791 713#define SPRN_PMC6 792 --- 160 unchanged lines hidden (view full) --- 874 * - SPRG2 scratch for exception vectors 875 * - SPRG3 CPU and NUMA node for VDSO getcpu (user visible) 876 * - HSPRG0 stores PACA in HV mode 877 * - HSPRG1 scratch for "HV" exceptions 878 * 879 * 64-bit embedded 880 * - SPRG0 generic exception scratch 881 * - SPRG2 TLB exception stack | 717#define SPRN_WORT 895 /* Workload optimization register - thread */ 718 719#define SPRN_PMC1 787 720#define SPRN_PMC2 788 721#define SPRN_PMC3 789 722#define SPRN_PMC4 790 723#define SPRN_PMC5 791 724#define SPRN_PMC6 792 --- 160 unchanged lines hidden (view full) --- 885 * - SPRG2 scratch for exception vectors 886 * - SPRG3 CPU and NUMA node for VDSO getcpu (user visible) 887 * - HSPRG0 stores PACA in HV mode 888 * - HSPRG1 scratch for "HV" exceptions 889 * 890 * 64-bit embedded 891 * - SPRG0 generic exception scratch 892 * - SPRG2 TLB exception stack |
| 882 * - SPRG3 critical exception scratch and 883 * CPU and NUMA node for VDSO getcpu (user visible) | 893 * - SPRG3 critical exception scratch (user visible, sorry!) |
| 884 * - SPRG4 unused (user visible) 885 * - SPRG6 TLB miss scratch (user visible, sorry !) | 894 * - SPRG4 unused (user visible) 895 * - SPRG6 TLB miss scratch (user visible, sorry !) |
| 886 * - SPRG7 critical exception scratch | 896 * - SPRG7 CPU and NUMA node for VDSO getcpu (user visible) |
| 887 * - SPRG8 machine check exception scratch 888 * - SPRG9 debug exception scratch 889 * 890 * All 32-bit: 891 * - SPRG3 current thread_info pointer 892 * (virtual on BookE, physical on others) 893 * 894 * 32-bit classic: --- 40 unchanged lines hidden (view full) --- 935#else 936#define SPRN_SPRG_THREAD SPRN_SPRG3 937#endif 938 939#ifdef CONFIG_PPC_BOOK3S_64 940#define SPRN_SPRG_SCRATCH0 SPRN_SPRG2 941#define SPRN_SPRG_HPACA SPRN_HSPRG0 942#define SPRN_SPRG_HSCRATCH0 SPRN_HSPRG1 | 897 * - SPRG8 machine check exception scratch 898 * - SPRG9 debug exception scratch 899 * 900 * All 32-bit: 901 * - SPRG3 current thread_info pointer 902 * (virtual on BookE, physical on others) 903 * 904 * 32-bit classic: --- 40 unchanged lines hidden (view full) --- 945#else 946#define SPRN_SPRG_THREAD SPRN_SPRG3 947#endif 948 949#ifdef CONFIG_PPC_BOOK3S_64 950#define SPRN_SPRG_SCRATCH0 SPRN_SPRG2 951#define SPRN_SPRG_HPACA SPRN_HSPRG0 952#define SPRN_SPRG_HSCRATCH0 SPRN_HSPRG1 |
| 953#define SPRN_SPRG_VDSO_READ SPRN_USPRG3 954#define SPRN_SPRG_VDSO_WRITE SPRN_SPRG3 |
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| 943 944#define GET_PACA(rX) \ 945 BEGIN_FTR_SECTION_NESTED(66); \ 946 mfspr rX,SPRN_SPRG_PACA; \ 947 FTR_SECTION_ELSE_NESTED(66); \ 948 mfspr rX,SPRN_SPRG_HPACA; \ 949 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66) 950 --- 27 unchanged lines hidden (view full) --- 978#ifdef CONFIG_PPC_BOOK3E_64 979#define SPRN_SPRG_MC_SCRATCH SPRN_SPRG8 980#define SPRN_SPRG_CRIT_SCRATCH SPRN_SPRG3 981#define SPRN_SPRG_DBG_SCRATCH SPRN_SPRG9 982#define SPRN_SPRG_TLB_EXFRAME SPRN_SPRG2 983#define SPRN_SPRG_TLB_SCRATCH SPRN_SPRG6 984#define SPRN_SPRG_GEN_SCRATCH SPRN_SPRG0 985#define SPRN_SPRG_GDBELL_SCRATCH SPRN_SPRG_GEN_SCRATCH | 955 956#define GET_PACA(rX) \ 957 BEGIN_FTR_SECTION_NESTED(66); \ 958 mfspr rX,SPRN_SPRG_PACA; \ 959 FTR_SECTION_ELSE_NESTED(66); \ 960 mfspr rX,SPRN_SPRG_HPACA; \ 961 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66) 962 --- 27 unchanged lines hidden (view full) --- 990#ifdef CONFIG_PPC_BOOK3E_64 991#define SPRN_SPRG_MC_SCRATCH SPRN_SPRG8 992#define SPRN_SPRG_CRIT_SCRATCH SPRN_SPRG3 993#define SPRN_SPRG_DBG_SCRATCH SPRN_SPRG9 994#define SPRN_SPRG_TLB_EXFRAME SPRN_SPRG2 995#define SPRN_SPRG_TLB_SCRATCH SPRN_SPRG6 996#define SPRN_SPRG_GEN_SCRATCH SPRN_SPRG0 997#define SPRN_SPRG_GDBELL_SCRATCH SPRN_SPRG_GEN_SCRATCH |
| 998#define SPRN_SPRG_VDSO_READ SPRN_USPRG7 999#define SPRN_SPRG_VDSO_WRITE SPRN_SPRG7 |
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| 986 987#define SET_PACA(rX) mtspr SPRN_SPRG_PACA,rX 988#define GET_PACA(rX) mfspr rX,SPRN_SPRG_PACA 989 990#endif 991 992#ifdef CONFIG_PPC_BOOK3S_32 993#define SPRN_SPRG_SCRATCH0 SPRN_SPRG0 --- 103 unchanged lines hidden (view full) --- 1097#define PVR_750P PVR_740P 1098#define PVR_7400 0x000C0000 1099#define PVR_7410 0x800C0000 1100#define PVR_7450 0x80000000 1101#define PVR_8540 0x80200000 1102#define PVR_8560 0x80200000 1103#define PVR_VER_E500V1 0x8020 1104#define PVR_VER_E500V2 0x8021 | 1000 1001#define SET_PACA(rX) mtspr SPRN_SPRG_PACA,rX 1002#define GET_PACA(rX) mfspr rX,SPRN_SPRG_PACA 1003 1004#endif 1005 1006#ifdef CONFIG_PPC_BOOK3S_32 1007#define SPRN_SPRG_SCRATCH0 SPRN_SPRG0 --- 103 unchanged lines hidden (view full) --- 1111#define PVR_750P PVR_740P 1112#define PVR_7400 0x000C0000 1113#define PVR_7410 0x800C0000 1114#define PVR_7450 0x80000000 1115#define PVR_8540 0x80200000 1116#define PVR_8560 0x80200000 1117#define PVR_VER_E500V1 0x8020 1118#define PVR_VER_E500V2 0x8021 |
| 1119#define PVR_VER_E500MC 0x8023 1120#define PVR_VER_E5500 0x8024 |
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| 1105#define PVR_VER_E6500 0x8040 1106 1107/* 1108 * For the 8xx processors, all of them report the same PVR family for 1109 * the PowerPC core. The various versions of these processors must be 1110 * differentiated by the version number in the Communication Processor 1111 * Module (CPM). 1112 */ --- 132 unchanged lines hidden --- | 1121#define PVR_VER_E6500 0x8040 1122 1123/* 1124 * For the 8xx processors, all of them report the same PVR family for 1125 * the PowerPC core. The various versions of these processors must be 1126 * differentiated by the version number in the Communication Processor 1127 * Module (CPM). 1128 */ --- 132 unchanged lines hidden --- |