| reg.h (2ac5e38ea4203852d6e99edd3cf11f044b0a409f) | reg.h (d7cceda96badc1bd444cff27ab9c375a1277c1e3) |
|---|---|
| 1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Contains the definition of registers common to all PowerPC variants. 4 * If a register definition has been changed in a different PowerPC 5 * variant, we will case it in #ifndef XXX ... #endif, and have the 6 * number used in the Programming Environments Manual For 32-Bit 7 * Implementations of the PowerPC Architecture (a.k.a. Green Book) here. 8 */ --- 568 unchanged lines hidden (view full) --- 577#define HID0_POWER8_1TO2LPAR __MASK(52) 578#define HID0_POWER8_1TO4LPAR __MASK(51) 579#define HID0_POWER8_DYNLPARDIS __MASK(48) 580 581/* POWER9 HID0 bits */ 582#define HID0_POWER9_RADIX __MASK(63 - 8) 583 584#define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */ | 1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Contains the definition of registers common to all PowerPC variants. 4 * If a register definition has been changed in a different PowerPC 5 * variant, we will case it in #ifndef XXX ... #endif, and have the 6 * number used in the Programming Environments Manual For 32-Bit 7 * Implementations of the PowerPC Architecture (a.k.a. Green Book) here. 8 */ --- 568 unchanged lines hidden (view full) --- 577#define HID0_POWER8_1TO2LPAR __MASK(52) 578#define HID0_POWER8_1TO4LPAR __MASK(51) 579#define HID0_POWER8_DYNLPARDIS __MASK(48) 580 581/* POWER9 HID0 bits */ 582#define HID0_POWER9_RADIX __MASK(63 - 8) 583 584#define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */ |
| 585#ifdef CONFIG_6xx | 585#ifdef CONFIG_PPC_BOOK3S_32 |
| 586#define HID1_EMCP (1<<31) /* 7450 Machine Check Pin Enable */ 587#define HID1_DFS (1<<22) /* 7447A Dynamic Frequency Scaling */ 588#define HID1_PC0 (1<<16) /* 7450 PLL_CFG[0] */ 589#define HID1_PC1 (1<<15) /* 7450 PLL_CFG[1] */ 590#define HID1_PC2 (1<<14) /* 7450 PLL_CFG[2] */ 591#define HID1_PC3 (1<<13) /* 7450 PLL_CFG[3] */ 592#define HID1_SYNCBE (1<<11) /* 7450 ABE for sync, eieio */ 593#define HID1_ABE (1<<10) /* 7450 Address Broadcast Enable */ --- 857 unchanged lines hidden --- | 586#define HID1_EMCP (1<<31) /* 7450 Machine Check Pin Enable */ 587#define HID1_DFS (1<<22) /* 7447A Dynamic Frequency Scaling */ 588#define HID1_PC0 (1<<16) /* 7450 PLL_CFG[0] */ 589#define HID1_PC1 (1<<15) /* 7450 PLL_CFG[1] */ 590#define HID1_PC2 (1<<14) /* 7450 PLL_CFG[2] */ 591#define HID1_PC3 (1<<13) /* 7450 PLL_CFG[3] */ 592#define HID1_SYNCBE (1<<11) /* 7450 ABE for sync, eieio */ 593#define HID1_ABE (1<<10) /* 7450 Address Broadcast Enable */ --- 857 unchanged lines hidden --- |