| processor.h (303e6a9ddcdc168e92253c78cdb4bbe1e10d78b3) | processor.h (74c6881019b7d56c327fffc268d97adb5eb1b4f9) |
|---|---|
| 1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2#ifndef _ASM_POWERPC_PROCESSOR_H 3#define _ASM_POWERPC_PROCESSOR_H 4 5/* 6 * Copyright (C) 2001 PPC 64 Team, IBM Corp 7 */ 8 --- 171 unchanged lines hidden (view full) --- 180 int fpexc_mode; /* floating-point exception mode */ 181 unsigned int align_ctl; /* alignment handling control */ 182#ifdef CONFIG_HAVE_HW_BREAKPOINT 183 struct perf_event *ptrace_bps[HBP_NUM_MAX]; 184 /* 185 * Helps identify source of single-step exception and subsequent 186 * hw-breakpoint enablement 187 */ | 1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2#ifndef _ASM_POWERPC_PROCESSOR_H 3#define _ASM_POWERPC_PROCESSOR_H 4 5/* 6 * Copyright (C) 2001 PPC 64 Team, IBM Corp 7 */ 8 --- 171 unchanged lines hidden (view full) --- 180 int fpexc_mode; /* floating-point exception mode */ 181 unsigned int align_ctl; /* alignment handling control */ 182#ifdef CONFIG_HAVE_HW_BREAKPOINT 183 struct perf_event *ptrace_bps[HBP_NUM_MAX]; 184 /* 185 * Helps identify source of single-step exception and subsequent 186 * hw-breakpoint enablement 187 */ |
| 188 struct perf_event *last_hit_ubp; | 188 struct perf_event *last_hit_ubp[HBP_NUM_MAX]; |
| 189#endif /* CONFIG_HAVE_HW_BREAKPOINT */ 190 struct arch_hw_breakpoint hw_brk[HBP_NUM_MAX]; /* hardware breakpoint info */ 191 unsigned long trap_nr; /* last trap # on this thread */ 192 u8 load_slb; /* Ages out SLB preload cache entries */ 193 u8 load_fp; 194#ifdef CONFIG_ALTIVEC 195 u8 load_vec; 196 struct thread_vr_state vr_state; --- 261 unchanged lines hidden --- | 189#endif /* CONFIG_HAVE_HW_BREAKPOINT */ 190 struct arch_hw_breakpoint hw_brk[HBP_NUM_MAX]; /* hardware breakpoint info */ 191 unsigned long trap_nr; /* last trap # on this thread */ 192 u8 load_slb; /* Ages out SLB preload cache entries */ 193 u8 load_fp; 194#ifdef CONFIG_ALTIVEC 195 u8 load_vec; 196 struct thread_vr_state vr_state; --- 261 unchanged lines hidden --- |