mpic.h (e7a98675caf272a11dc1012c7a8c6c00cab09f5b) mpic.h (be8bec56dfac0574c4c08a50cd37e09bea941e3f)
1#ifndef _ASM_POWERPC_MPIC_H
2#define _ASM_POWERPC_MPIC_H
3#ifdef __KERNEL__
4
5#include <linux/irq.h>
6#include <asm/dcr.h>
7#include <asm/msi_bitmap.h>
8

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329/*
330 * MPIC flags (passed to mpic_alloc)
331 *
332 * The top 4 bits contain an MPIC bhw id that is used to index the
333 * register offsets and some masks when CONFIG_MPIC_WEIRD is set.
334 * Note setting any ID (leaving those bits to 0) means standard MPIC
335 */
336
1#ifndef _ASM_POWERPC_MPIC_H
2#define _ASM_POWERPC_MPIC_H
3#ifdef __KERNEL__
4
5#include <linux/irq.h>
6#include <asm/dcr.h>
7#include <asm/msi_bitmap.h>
8

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329/*
330 * MPIC flags (passed to mpic_alloc)
331 *
332 * The top 4 bits contain an MPIC bhw id that is used to index the
333 * register offsets and some masks when CONFIG_MPIC_WEIRD is set.
334 * Note setting any ID (leaving those bits to 0) means standard MPIC
335 */
336
337/* This is the primary controller, only that one has IPIs and
338 * has afinity control. A non-primary MPIC always uses CPU0
339 * registers only
337/*
338 * This is a secondary ("chained") controller; it only uses the CPU0
339 * registers. Primary controllers have IPIs and affinity control.
340 */
340 */
341#define MPIC_PRIMARY 0x00000001
341#define MPIC_SECONDARY 0x00000001
342
343/* Set this for a big-endian MPIC */
344#define MPIC_BIG_ENDIAN 0x00000002
345/* Broken U3 MPIC */
346#define MPIC_U3_HT_IRQS 0x00000004
347/* Broken IPI registers (autodetected) */
348#define MPIC_BROKEN_IPI 0x00000008
349/* MPIC wants a reset */

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343/* Set this for a big-endian MPIC */
344#define MPIC_BIG_ENDIAN 0x00000002
345/* Broken U3 MPIC */
346#define MPIC_U3_HT_IRQS 0x00000004
347/* Broken IPI registers (autodetected) */
348#define MPIC_BROKEN_IPI 0x00000008
349/* MPIC wants a reset */

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