mpc5121.h (ecd740c6f2f092b90b95fa35f757973589eaaca2) mpc5121.h (1a4bb93f795502e7e8350d4af1aa5909f15ffc28)
1/*
2 * MPC5121 Prototypes and definitions
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2.
6 */
7
8#ifndef __ASM_POWERPC_MPC5121_H__

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55 u32 burst_ctrl; /* CS Burst Control Register */
56 u32 deadcycle_ctrl; /* CS Deadcycle Control Register */
57 u32 holdcycle_ctrl; /* CS Holdcycle Control Register */
58 u32 alt; /* Address Latch Timing Register */
59};
60
61int mpc512x_cs_config(unsigned int cs, u32 val);
62
1/*
2 * MPC5121 Prototypes and definitions
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2.
6 */
7
8#ifndef __ASM_POWERPC_MPC5121_H__

--- 46 unchanged lines hidden (view full) ---

55 u32 burst_ctrl; /* CS Burst Control Register */
56 u32 deadcycle_ctrl; /* CS Deadcycle Control Register */
57 u32 holdcycle_ctrl; /* CS Holdcycle Control Register */
58 u32 alt; /* Address Latch Timing Register */
59};
60
61int mpc512x_cs_config(unsigned int cs, u32 val);
62
63/*
64 * SCLPC Module (LPB FIFO)
65 */
66struct mpc512x_lpbfifo {
67 u32 pkt_size; /* SCLPC Packet Size Register */
68 u32 start_addr; /* SCLPC Start Address Register */
69 u32 ctrl; /* SCLPC Control Register */
70 u32 enable; /* SCLPC Enable Register */
71 u32 reserved1;
72 u32 status; /* SCLPC Status Register */
73 u32 bytes_done; /* SCLPC Bytes Done Register */
74 u32 emb_sc; /* EMB Share Counter Register */
75 u32 emb_pc; /* EMB Pause Control Register */
76 u32 reserved2[7];
77 u32 data_word; /* LPC RX/TX FIFO Data Word Register */
78 u32 fifo_status; /* LPC RX/TX FIFO Status Register */
79 u32 fifo_ctrl; /* LPC RX/TX FIFO Control Register */
80 u32 fifo_alarm; /* LPC RX/TX FIFO Alarm Register */
81};
82
83#define MPC512X_SCLPC_START (1 << 31)
84#define MPC512X_SCLPC_CS(x) (((x) & 0x7) << 24)
85#define MPC512X_SCLPC_FLUSH (1 << 17)
86#define MPC512X_SCLPC_READ (1 << 16)
87#define MPC512X_SCLPC_DAI (1 << 8)
88#define MPC512X_SCLPC_BPT(x) ((x) & 0x3f)
89#define MPC512X_SCLPC_RESET (1 << 24)
90#define MPC512X_SCLPC_FIFO_RESET (1 << 16)
91#define MPC512X_SCLPC_ABORT_INT_ENABLE (1 << 9)
92#define MPC512X_SCLPC_NORM_INT_ENABLE (1 << 8)
93#define MPC512X_SCLPC_ENABLE (1 << 0)
94#define MPC512X_SCLPC_SUCCESS (1 << 24)
95#define MPC512X_SCLPC_FIFO_CTRL(x) (((x) & 0x7) << 24)
96#define MPC512X_SCLPC_FIFO_ALARM(x) ((x) & 0x3ff)
97
98enum lpb_dev_portsize {
99 LPB_DEV_PORTSIZE_UNDEFINED = 0,
100 LPB_DEV_PORTSIZE_1_BYTE = 1,
101 LPB_DEV_PORTSIZE_2_BYTES = 2,
102 LPB_DEV_PORTSIZE_4_BYTES = 4,
103 LPB_DEV_PORTSIZE_8_BYTES = 8
104};
105
106enum mpc512x_lpbfifo_req_dir {
107 MPC512X_LPBFIFO_REQ_DIR_READ,
108 MPC512X_LPBFIFO_REQ_DIR_WRITE
109};
110
111struct mpc512x_lpbfifo_request {
112 phys_addr_t dev_phys_addr; /* physical address of some device on LPB */
113 void *ram_virt_addr; /* virtual address of some region in RAM */
114 u32 size;
115 enum lpb_dev_portsize portsize;
116 enum mpc512x_lpbfifo_req_dir dir;
117 void (*callback)(struct mpc512x_lpbfifo_request *);
118};
119
120int mpc512x_lpbfifo_submit(struct mpc512x_lpbfifo_request *req);
121
63#endif /* __ASM_POWERPC_MPC5121_H__ */
122#endif /* __ASM_POWERPC_MPC5121_H__ */