cputable.h (03068ff131c0a565e2cb26303a0df63467136723) cputable.h (24cc67de62eebbda3ce0c46bdd56582c00dccd03)
1#ifndef __ASM_POWERPC_CPUTABLE_H
2#define __ASM_POWERPC_CPUTABLE_H
3
4#define PPC_FEATURE_32 0x80000000
5#define PPC_FEATURE_64 0x40000000
6#define PPC_FEATURE_601_INSTR 0x20000000
7#define PPC_FEATURE_HAS_ALTIVEC 0x10000000
8#define PPC_FEATURE_HAS_FPU 0x08000000

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176#define LONG_ASM_CONST(x) ASM_CONST(x)
177#else
178#define LONG_ASM_CONST(x) 0
179#endif
180
181#define CPU_FTR_SLB LONG_ASM_CONST(0x0000000100000000)
182#define CPU_FTR_16M_PAGE LONG_ASM_CONST(0x0000000200000000)
183#define CPU_FTR_TLBIEL LONG_ASM_CONST(0x0000000400000000)
1#ifndef __ASM_POWERPC_CPUTABLE_H
2#define __ASM_POWERPC_CPUTABLE_H
3
4#define PPC_FEATURE_32 0x80000000
5#define PPC_FEATURE_64 0x40000000
6#define PPC_FEATURE_601_INSTR 0x20000000
7#define PPC_FEATURE_HAS_ALTIVEC 0x10000000
8#define PPC_FEATURE_HAS_FPU 0x08000000

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176#define LONG_ASM_CONST(x) ASM_CONST(x)
177#else
178#define LONG_ASM_CONST(x) 0
179#endif
180
181#define CPU_FTR_SLB LONG_ASM_CONST(0x0000000100000000)
182#define CPU_FTR_16M_PAGE LONG_ASM_CONST(0x0000000200000000)
183#define CPU_FTR_TLBIEL LONG_ASM_CONST(0x0000000400000000)
184#define CPU_FTR_HVMODE_206 LONG_ASM_CONST(0x0000000800000000)
184#define CPU_FTR_IABR LONG_ASM_CONST(0x0000002000000000)
185#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000004000000000)
186#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000008000000000)
187#define CPU_FTR_SMT LONG_ASM_CONST(0x0000010000000000)
188#define CPU_FTR_LOCKLESS_TLBIE LONG_ASM_CONST(0x0000040000000000)
189#define CPU_FTR_CI_LARGE_PAGE LONG_ASM_CONST(0x0000100000000000)
190#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000200000000000)
191#define CPU_FTR_PURR LONG_ASM_CONST(0x0000400000000000)

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413#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
414 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
415 CPU_FTR_MMCRA | CPU_FTR_SMT | \
416 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
417 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
418 CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \
419 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB)
420#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
185#define CPU_FTR_IABR LONG_ASM_CONST(0x0000002000000000)
186#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000004000000000)
187#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000008000000000)
188#define CPU_FTR_SMT LONG_ASM_CONST(0x0000010000000000)
189#define CPU_FTR_LOCKLESS_TLBIE LONG_ASM_CONST(0x0000040000000000)
190#define CPU_FTR_CI_LARGE_PAGE LONG_ASM_CONST(0x0000100000000000)
191#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000200000000000)
192#define CPU_FTR_PURR LONG_ASM_CONST(0x0000400000000000)

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414#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
415 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
416 CPU_FTR_MMCRA | CPU_FTR_SMT | \
417 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
418 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
419 CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \
420 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB)
421#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
421 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
422 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_HVMODE_206 |\
422 CPU_FTR_MMCRA | CPU_FTR_SMT | \
423 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
424 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
425 CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \
426 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD)
427#define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
428 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
429 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \

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423 CPU_FTR_MMCRA | CPU_FTR_SMT | \
424 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
425 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
426 CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \
427 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD)
428#define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
429 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
430 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \

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