| radix.h (1136fa0c07de570dc17858745af8be169d1440ba) | radix.h (41b7a347bf1491e7300563bb224432608b41f62a) |
|---|---|
| 1/* SPDX-License-Identifier: GPL-2.0 */ 2#ifndef _ASM_POWERPC_PGTABLE_RADIX_H 3#define _ASM_POWERPC_PGTABLE_RADIX_H 4 5#include <asm/asm-const.h> 6 7#ifndef __ASSEMBLY__ 8#include <asm/cmpxchg.h> --- 21 unchanged lines hidden (view full) --- 30/* Don't have anything in the reserved bits and leaf bits */ 31#define RADIX_PMD_BAD_BITS 0x60000000000000e0UL 32#define RADIX_PUD_BAD_BITS 0x60000000000000e0UL 33#define RADIX_P4D_BAD_BITS 0x60000000000000e0UL 34 35#define RADIX_PMD_SHIFT (PAGE_SHIFT + RADIX_PTE_INDEX_SIZE) 36#define RADIX_PUD_SHIFT (RADIX_PMD_SHIFT + RADIX_PMD_INDEX_SIZE) 37#define RADIX_PGD_SHIFT (RADIX_PUD_SHIFT + RADIX_PUD_INDEX_SIZE) | 1/* SPDX-License-Identifier: GPL-2.0 */ 2#ifndef _ASM_POWERPC_PGTABLE_RADIX_H 3#define _ASM_POWERPC_PGTABLE_RADIX_H 4 5#include <asm/asm-const.h> 6 7#ifndef __ASSEMBLY__ 8#include <asm/cmpxchg.h> --- 21 unchanged lines hidden (view full) --- 30/* Don't have anything in the reserved bits and leaf bits */ 31#define RADIX_PMD_BAD_BITS 0x60000000000000e0UL 32#define RADIX_PUD_BAD_BITS 0x60000000000000e0UL 33#define RADIX_P4D_BAD_BITS 0x60000000000000e0UL 34 35#define RADIX_PMD_SHIFT (PAGE_SHIFT + RADIX_PTE_INDEX_SIZE) 36#define RADIX_PUD_SHIFT (RADIX_PMD_SHIFT + RADIX_PMD_INDEX_SIZE) 37#define RADIX_PGD_SHIFT (RADIX_PUD_SHIFT + RADIX_PUD_INDEX_SIZE) |
| 38 39#define R_PTRS_PER_PTE (1 << RADIX_PTE_INDEX_SIZE) 40#define R_PTRS_PER_PMD (1 << RADIX_PMD_INDEX_SIZE) 41#define R_PTRS_PER_PUD (1 << RADIX_PUD_INDEX_SIZE) 42 |
|
| 38/* 39 * Size of EA range mapped by our pagetables. 40 */ 41#define RADIX_PGTABLE_EADDR_SIZE (RADIX_PTE_INDEX_SIZE + RADIX_PMD_INDEX_SIZE + \ 42 RADIX_PUD_INDEX_SIZE + RADIX_PGD_INDEX_SIZE + PAGE_SHIFT) 43#define RADIX_PGTABLE_RANGE (ASM_CONST(1) << RADIX_PGTABLE_EADDR_SIZE) 44 45/* --- 17 unchanged lines hidden (view full) --- 63 * 0b01......+------------------+ 64 * | | 65 * | 0 quadrant | 66 * | | 67 * 0b00......+------------------+ 68 * 69 * 70 * 3rd quadrant expanded: | 43/* 44 * Size of EA range mapped by our pagetables. 45 */ 46#define RADIX_PGTABLE_EADDR_SIZE (RADIX_PTE_INDEX_SIZE + RADIX_PMD_INDEX_SIZE + \ 47 RADIX_PUD_INDEX_SIZE + RADIX_PGD_INDEX_SIZE + PAGE_SHIFT) 48#define RADIX_PGTABLE_RANGE (ASM_CONST(1) << RADIX_PGTABLE_EADDR_SIZE) 49 50/* --- 17 unchanged lines hidden (view full) --- 68 * 0b01......+------------------+ 69 * | | 70 * | 0 quadrant | 71 * | | 72 * 0b00......+------------------+ 73 * 74 * 75 * 3rd quadrant expanded: |
| 71 * +------------------------------+ | 76 * +------------------------------+ Highest address (0xc010000000000000) 77 * +------------------------------+ KASAN shadow end (0xc00fc00000000000) |
| 72 * | | 73 * | | | 78 * | | 79 * | | |
| 80 * +------------------------------+ Kernel vmemmap end/shadow start (0xc00e000000000000) |
|
| 74 * | | | 81 * | | |
| 75 * +------------------------------+ Kernel vmemmap end (0xc010000000000000) 76 * | | | |
| 77 * | 512TB | 78 * | | 79 * +------------------------------+ Kernel IO map end/vmemap start 80 * | | 81 * | 512TB | 82 * | | 83 * +------------------------------+ Kernel vmap end/ IO map start 84 * | | 85 * | 512TB | 86 * | | 87 * +------------------------------+ Kernel virt start (0xc008000000000000) 88 * | | 89 * | | 90 * | | 91 * +------------------------------+ Kernel linear (0xc.....) 92 */ 93 | 82 * | 512TB | 83 * | | 84 * +------------------------------+ Kernel IO map end/vmemap start 85 * | | 86 * | 512TB | 87 * | | 88 * +------------------------------+ Kernel vmap end/ IO map start 89 * | | 90 * | 512TB | 91 * | | 92 * +------------------------------+ Kernel virt start (0xc008000000000000) 93 * | | 94 * | | 95 * | | 96 * +------------------------------+ Kernel linear (0xc.....) 97 */ 98 |
| 99/* For the sizes of the shadow area, see kasan.h */ |
|
| 94 95/* 96 * If we store section details in page->flags we can't increase the MAX_PHYSMEM_BITS 97 * if we increase SECTIONS_WIDTH we will not store node details in page->flags and 98 * page_to_nid does a page->section->node lookup 99 * Hence only increase for VMEMMAP. Further depending on SPARSEMEM_EXTREME reduce 100 * memory requirements with large number of sections. 101 * 51 bits is the max physical real address on POWER9 --- 222 unchanged lines hidden --- | 100 101/* 102 * If we store section details in page->flags we can't increase the MAX_PHYSMEM_BITS 103 * if we increase SECTIONS_WIDTH we will not store node details in page->flags and 104 * page_to_nid does a page->section->node lookup 105 * Hence only increase for VMEMMAP. Further depending on SPARSEMEM_EXTREME reduce 106 * memory requirements with large number of sections. 107 * 51 bits is the max physical real address on POWER9 --- 222 unchanged lines hidden --- |