tqm8560.dts (7bee946358c3cb957d4aa648fc5ab3cad0b232d0) tqm8560.dts (fe671772ab1bf5624f2c4dbe2295e6ebeb8055fc)
1/*
2 * TQM 8560 Device Tree Source
3 *
4 * Copyright 2008 Freescale Semiconductor Inc.
5 * Copyright 2008 Wolfgang Grandegger <wg@grandegger.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the

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55 #size-cells = <1>;
56 device_type = "soc";
57 ranges = <0x0 0xe0000000 0x100000>;
58 reg = <0xe0000000 0x200>;
59 bus-frequency = <0>;
60 compatible = "fsl,mpc8560-immr", "simple-bus";
61
62 memory-controller@2000 {
1/*
2 * TQM 8560 Device Tree Source
3 *
4 * Copyright 2008 Freescale Semiconductor Inc.
5 * Copyright 2008 Wolfgang Grandegger <wg@grandegger.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the

--- 46 unchanged lines hidden (view full) ---

55 #size-cells = <1>;
56 device_type = "soc";
57 ranges = <0x0 0xe0000000 0x100000>;
58 reg = <0xe0000000 0x200>;
59 bus-frequency = <0>;
60 compatible = "fsl,mpc8560-immr", "simple-bus";
61
62 memory-controller@2000 {
63 compatible = "fsl,8540-memory-controller";
63 compatible = "fsl,mpc8540-memory-controller";
64 reg = <0x2000 0x1000>;
65 interrupt-parent = <&mpic>;
66 interrupts = <18 2>;
67 };
68
69 L2: l2-cache-controller@20000 {
64 reg = <0x2000 0x1000>;
65 interrupt-parent = <&mpic>;
66 interrupts = <18 2>;
67 };
68
69 L2: l2-cache-controller@20000 {
70 compatible = "fsl,8540-l2-cache-controller";
70 compatible = "fsl,mpc8540-l2-cache-controller";
71 reg = <0x20000 0x1000>;
72 cache-line-size = <32>;
73 cache-size = <0x40000>; // L2, 256K
74 interrupt-parent = <&mpic>;
75 interrupts = <16 2>;
76 };
77
78 i2c@3000 {

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71 reg = <0x20000 0x1000>;
72 cache-line-size = <32>;
73 cache-size = <0x40000>; // L2, 256K
74 interrupt-parent = <&mpic>;
75 interrupts = <16 2>;
76 };
77
78 i2c@3000 {

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