rainier.dts (96916090f488986a4ebb8e9ffa6a3b50881d5ccd) rainier.dts (71f349799b34c8b6ce3df42126b4de6cfa16456d)
1/*
2 * Device Tree Source for AMCC Rainier
3 *
4 * Based on Sequoia code
5 * Copyright (c) 2007 MontaVista Software, Inc.
6 *
7 * FIXME: Draft only!
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without
11 * any warranty of any kind, whether express or implied.
12 *
13 */
14
1/*
2 * Device Tree Source for AMCC Rainier
3 *
4 * Based on Sequoia code
5 * Copyright (c) 2007 MontaVista Software, Inc.
6 *
7 * FIXME: Draft only!
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without
11 * any warranty of any kind, whether express or implied.
12 *
13 */
14
15/dts-v1/;
16
15/ {
16 #address-cells = <2>;
17 #size-cells = <1>;
18 model = "amcc,rainier";
19 compatible = "amcc,rainier";
17/ {
18 #address-cells = <2>;
19 #size-cells = <1>;
20 model = "amcc,rainier";
21 compatible = "amcc,rainier";
20 dcr-parent = <&/cpus/cpu@0>;
22 dcr-parent = <&{/cpus/cpu@0}>;
21
22 aliases {
23 ethernet0 = &EMAC0;
24 ethernet1 = &EMAC1;
25 serial0 = &UART0;
26 serial1 = &UART1;
27 serial2 = &UART2;
28 serial3 = &UART3;
29 };
30
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 cpu@0 {
36 device_type = "cpu";
37 model = "PowerPC,440GRx";
23
24 aliases {
25 ethernet0 = &EMAC0;
26 ethernet1 = &EMAC1;
27 serial0 = &UART0;
28 serial1 = &UART1;
29 serial2 = &UART2;
30 serial3 = &UART3;
31 };
32
33 cpus {
34 #address-cells = <1>;
35 #size-cells = <0>;
36
37 cpu@0 {
38 device_type = "cpu";
39 model = "PowerPC,440GRx";
38 reg = <0>;
40 reg = <0x00000000>;
39 clock-frequency = <0>; /* Filled in by zImage */
40 timebase-frequency = <0>; /* Filled in by zImage */
41 clock-frequency = <0>; /* Filled in by zImage */
42 timebase-frequency = <0>; /* Filled in by zImage */
41 i-cache-line-size = <20>;
42 d-cache-line-size = <20>;
43 i-cache-size = <8000>;
44 d-cache-size = <8000>;
43 i-cache-line-size = <32>;
44 d-cache-line-size = <32>;
45 i-cache-size = <32768>;
46 d-cache-size = <32768>;
45 dcr-controller;
46 dcr-access-method = "native";
47 };
48 };
49
50 memory {
51 device_type = "memory";
47 dcr-controller;
48 dcr-access-method = "native";
49 };
50 };
51
52 memory {
53 device_type = "memory";
52 reg = <0 0 0>; /* Filled in by zImage */
54 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by zImage */
53 };
54
55 UIC0: interrupt-controller0 {
56 compatible = "ibm,uic-440grx","ibm,uic";
57 interrupt-controller;
58 cell-index = <0>;
55 };
56
57 UIC0: interrupt-controller0 {
58 compatible = "ibm,uic-440grx","ibm,uic";
59 interrupt-controller;
60 cell-index = <0>;
59 dcr-reg = <0c0 009>;
61 dcr-reg = <0x0c0 0x009>;
60 #address-cells = <0>;
61 #size-cells = <0>;
62 #interrupt-cells = <2>;
63 };
64
65 UIC1: interrupt-controller1 {
66 compatible = "ibm,uic-440grx","ibm,uic";
67 interrupt-controller;
68 cell-index = <1>;
62 #address-cells = <0>;
63 #size-cells = <0>;
64 #interrupt-cells = <2>;
65 };
66
67 UIC1: interrupt-controller1 {
68 compatible = "ibm,uic-440grx","ibm,uic";
69 interrupt-controller;
70 cell-index = <1>;
69 dcr-reg = <0d0 009>;
71 dcr-reg = <0x0d0 0x009>;
70 #address-cells = <0>;
71 #size-cells = <0>;
72 #interrupt-cells = <2>;
72 #address-cells = <0>;
73 #size-cells = <0>;
74 #interrupt-cells = <2>;
73 interrupts = <1e 4 1f 4>; /* cascade */
75 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
74 interrupt-parent = <&UIC0>;
75 };
76
77 UIC2: interrupt-controller2 {
78 compatible = "ibm,uic-440grx","ibm,uic";
79 interrupt-controller;
80 cell-index = <2>;
76 interrupt-parent = <&UIC0>;
77 };
78
79 UIC2: interrupt-controller2 {
80 compatible = "ibm,uic-440grx","ibm,uic";
81 interrupt-controller;
82 cell-index = <2>;
81 dcr-reg = <0e0 009>;
83 dcr-reg = <0x0e0 0x009>;
82 #address-cells = <0>;
83 #size-cells = <0>;
84 #interrupt-cells = <2>;
84 #address-cells = <0>;
85 #size-cells = <0>;
86 #interrupt-cells = <2>;
85 interrupts = <1c 4 1d 4>; /* cascade */
87 interrupts = <0x1c 0x4 0x1d 0x4>; /* cascade */
86 interrupt-parent = <&UIC0>;
87 };
88
89 SDR0: sdr {
90 compatible = "ibm,sdr-440grx", "ibm,sdr-440ep";
88 interrupt-parent = <&UIC0>;
89 };
90
91 SDR0: sdr {
92 compatible = "ibm,sdr-440grx", "ibm,sdr-440ep";
91 dcr-reg = <00e 002>;
93 dcr-reg = <0x00e 0x002>;
92 };
93
94 CPR0: cpr {
95 compatible = "ibm,cpr-440grx", "ibm,cpr-440ep";
94 };
95
96 CPR0: cpr {
97 compatible = "ibm,cpr-440grx", "ibm,cpr-440ep";
96 dcr-reg = <00c 002>;
98 dcr-reg = <0x00c 0x002>;
97 };
98
99 plb {
100 compatible = "ibm,plb-440grx", "ibm,plb4";
101 #address-cells = <2>;
102 #size-cells = <1>;
103 ranges;
104 clock-frequency = <0>; /* Filled in by zImage */
105
106 SDRAM0: sdram {
107 compatible = "ibm,sdram-440grx", "ibm,sdram-44x-ddr2denali";
99 };
100
101 plb {
102 compatible = "ibm,plb-440grx", "ibm,plb4";
103 #address-cells = <2>;
104 #size-cells = <1>;
105 ranges;
106 clock-frequency = <0>; /* Filled in by zImage */
107
108 SDRAM0: sdram {
109 compatible = "ibm,sdram-440grx", "ibm,sdram-44x-ddr2denali";
108 dcr-reg = <010 2>;
110 dcr-reg = <0x010 0x002>;
109 };
110
111 DMA0: dma {
112 compatible = "ibm,dma-440grx", "ibm,dma-4xx";
111 };
112
113 DMA0: dma {
114 compatible = "ibm,dma-440grx", "ibm,dma-4xx";
113 dcr-reg = <100 027>;
115 dcr-reg = <0x100 0x027>;
114 };
115
116 MAL0: mcmal {
117 compatible = "ibm,mcmal-440grx", "ibm,mcmal2";
116 };
117
118 MAL0: mcmal {
119 compatible = "ibm,mcmal-440grx", "ibm,mcmal2";
118 dcr-reg = <180 62>;
120 dcr-reg = <0x180 0x062>;
119 num-tx-chans = <2>;
120 num-rx-chans = <2>;
121 interrupt-parent = <&MAL0>;
121 num-tx-chans = <2>;
122 num-rx-chans = <2>;
123 interrupt-parent = <&MAL0>;
122 interrupts = <0 1 2 3 4>;
124 interrupts = <0x0 0x1 0x2 0x3 0x4>;
123 #interrupt-cells = <1>;
124 #address-cells = <0>;
125 #size-cells = <0>;
125 #interrupt-cells = <1>;
126 #address-cells = <0>;
127 #size-cells = <0>;
126 interrupt-map = </*TXEOB*/ 0 &UIC0 a 4
127 /*RXEOB*/ 1 &UIC0 b 4
128 /*SERR*/ 2 &UIC1 0 4
129 /*TXDE*/ 3 &UIC1 1 4
130 /*RXDE*/ 4 &UIC1 2 4>;
131 interrupt-map-mask = <ffffffff>;
128 interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4
129 /*RXEOB*/ 0x1 &UIC0 0xb 0x4
130 /*SERR*/ 0x2 &UIC1 0x0 0x4
131 /*TXDE*/ 0x3 &UIC1 0x1 0x4
132 /*RXDE*/ 0x4 &UIC1 0x2 0x4>;
133 interrupt-map-mask = <0xffffffff>;
132 };
133
134 POB0: opb {
135 compatible = "ibm,opb-440grx", "ibm,opb";
136 #address-cells = <1>;
137 #size-cells = <1>;
134 };
135
136 POB0: opb {
137 compatible = "ibm,opb-440grx", "ibm,opb";
138 #address-cells = <1>;
139 #size-cells = <1>;
138 ranges = <00000000 1 00000000 80000000
139 80000000 1 80000000 80000000>;
140 ranges = <0x00000000 0x00000001 0x00000000 0x80000000
141 0x80000000 0x00000001 0x80000000 0x80000000>;
140 interrupt-parent = <&UIC1>;
142 interrupt-parent = <&UIC1>;
141 interrupts = <7 4>;
143 interrupts = <0x7 0x4>;
142 clock-frequency = <0>; /* Filled in by zImage */
143
144 EBC0: ebc {
145 compatible = "ibm,ebc-440grx", "ibm,ebc";
144 clock-frequency = <0>; /* Filled in by zImage */
145
146 EBC0: ebc {
147 compatible = "ibm,ebc-440grx", "ibm,ebc";
146 dcr-reg = <012 2>;
148 dcr-reg = <0x012 0x002>;
147 #address-cells = <2>;
148 #size-cells = <1>;
149 clock-frequency = <0>; /* Filled in by zImage */
149 #address-cells = <2>;
150 #size-cells = <1>;
151 clock-frequency = <0>; /* Filled in by zImage */
150 interrupts = <5 1>;
152 interrupts = <0x5 0x1>;
151 interrupt-parent = <&UIC1>;
152
153 nor_flash@0,0 {
154 compatible = "amd,s29gl256n", "cfi-flash";
155 bank-width = <2>;
153 interrupt-parent = <&UIC1>;
154
155 nor_flash@0,0 {
156 compatible = "amd,s29gl256n", "cfi-flash";
157 bank-width = <2>;
156 reg = <0 000000 4000000>;
158 reg = <0x00000000 0x00000000 0x04000000>;
157 #address-cells = <1>;
158 #size-cells = <1>;
159 partition@0 {
160 label = "Kernel";
159 #address-cells = <1>;
160 #size-cells = <1>;
161 partition@0 {
162 label = "Kernel";
161 reg = <0 180000>;
163 reg = <0x00000000 0x00180000>;
162 };
163 partition@180000 {
164 label = "ramdisk";
164 };
165 partition@180000 {
166 label = "ramdisk";
165 reg = <180000 200000>;
167 reg = <0x00180000 0x00200000>;
166 };
167 partition@380000 {
168 label = "file system";
168 };
169 partition@380000 {
170 label = "file system";
169 reg = <380000 3aa0000>;
171 reg = <0x00380000 0x03aa0000>;
170 };
171 partition@3e20000 {
172 label = "kozio";
172 };
173 partition@3e20000 {
174 label = "kozio";
173 reg = <3e20000 140000>;
175 reg = <0x03e20000 0x00140000>;
174 };
175 partition@3f60000 {
176 label = "env";
176 };
177 partition@3f60000 {
178 label = "env";
177 reg = <3f60000 40000>;
179 reg = <0x03f60000 0x00040000>;
178 };
179 partition@3fa0000 {
180 label = "u-boot";
180 };
181 partition@3fa0000 {
182 label = "u-boot";
181 reg = <3fa0000 60000>;
183 reg = <0x03fa0000 0x00060000>;
182 };
183 };
184
185 };
186
187 UART0: serial@ef600300 {
188 device_type = "serial";
189 compatible = "ns16550";
184 };
185 };
186
187 };
188
189 UART0: serial@ef600300 {
190 device_type = "serial";
191 compatible = "ns16550";
190 reg = <ef600300 8>;
191 virtual-reg = <ef600300>;
192 reg = <0xef600300 0x00000008>;
193 virtual-reg = <0xef600300>;
192 clock-frequency = <0>; /* Filled in by zImage */
194 clock-frequency = <0>; /* Filled in by zImage */
193 current-speed = <1c200>;
195 current-speed = <115200>;
194 interrupt-parent = <&UIC0>;
196 interrupt-parent = <&UIC0>;
195 interrupts = <0 4>;
197 interrupts = <0x0 0x4>;
196 };
197
198 UART1: serial@ef600400 {
199 device_type = "serial";
200 compatible = "ns16550";
198 };
199
200 UART1: serial@ef600400 {
201 device_type = "serial";
202 compatible = "ns16550";
201 reg = <ef600400 8>;
202 virtual-reg = <ef600400>;
203 reg = <0xef600400 0x00000008>;
204 virtual-reg = <0xef600400>;
203 clock-frequency = <0>;
204 current-speed = <0>;
205 interrupt-parent = <&UIC0>;
205 clock-frequency = <0>;
206 current-speed = <0>;
207 interrupt-parent = <&UIC0>;
206 interrupts = <1 4>;
208 interrupts = <0x1 0x4>;
207 };
208
209 UART2: serial@ef600500 {
210 device_type = "serial";
211 compatible = "ns16550";
209 };
210
211 UART2: serial@ef600500 {
212 device_type = "serial";
213 compatible = "ns16550";
212 reg = <ef600500 8>;
213 virtual-reg = <ef600500>;
214 reg = <0xef600500 0x00000008>;
215 virtual-reg = <0xef600500>;
214 clock-frequency = <0>;
215 current-speed = <0>;
216 interrupt-parent = <&UIC1>;
216 clock-frequency = <0>;
217 current-speed = <0>;
218 interrupt-parent = <&UIC1>;
217 interrupts = <3 4>;
219 interrupts = <0x3 0x4>;
218 };
219
220 UART3: serial@ef600600 {
221 device_type = "serial";
222 compatible = "ns16550";
220 };
221
222 UART3: serial@ef600600 {
223 device_type = "serial";
224 compatible = "ns16550";
223 reg = <ef600600 8>;
224 virtual-reg = <ef600600>;
225 reg = <0xef600600 0x00000008>;
226 virtual-reg = <0xef600600>;
225 clock-frequency = <0>;
226 current-speed = <0>;
227 interrupt-parent = <&UIC1>;
227 clock-frequency = <0>;
228 current-speed = <0>;
229 interrupt-parent = <&UIC1>;
228 interrupts = <4 4>;
230 interrupts = <0x4 0x4>;
229 };
230
231 IIC0: i2c@ef600700 {
232 compatible = "ibm,iic-440grx", "ibm,iic";
231 };
232
233 IIC0: i2c@ef600700 {
234 compatible = "ibm,iic-440grx", "ibm,iic";
233 reg = <ef600700 14>;
235 reg = <0xef600700 0x00000014>;
234 interrupt-parent = <&UIC0>;
236 interrupt-parent = <&UIC0>;
235 interrupts = <2 4>;
237 interrupts = <0x2 0x4>;
236 };
237
238 IIC1: i2c@ef600800 {
239 compatible = "ibm,iic-440grx", "ibm,iic";
238 };
239
240 IIC1: i2c@ef600800 {
241 compatible = "ibm,iic-440grx", "ibm,iic";
240 reg = <ef600800 14>;
242 reg = <0xef600800 0x00000014>;
241 interrupt-parent = <&UIC0>;
243 interrupt-parent = <&UIC0>;
242 interrupts = <7 4>;
244 interrupts = <0x7 0x4>;
243 };
244
245 ZMII0: emac-zmii@ef600d00 {
246 compatible = "ibm,zmii-440grx", "ibm,zmii";
245 };
246
247 ZMII0: emac-zmii@ef600d00 {
248 compatible = "ibm,zmii-440grx", "ibm,zmii";
247 reg = <ef600d00 c>;
249 reg = <0xef600d00 0x0000000c>;
248 };
249
250 RGMII0: emac-rgmii@ef601000 {
251 compatible = "ibm,rgmii-440grx", "ibm,rgmii";
250 };
251
252 RGMII0: emac-rgmii@ef601000 {
253 compatible = "ibm,rgmii-440grx", "ibm,rgmii";
252 reg = <ef601000 8>;
254 reg = <0xef601000 0x00000008>;
253 has-mdio;
254 };
255
256 EMAC0: ethernet@ef600e00 {
257 device_type = "network";
258 compatible = "ibm,emac-440grx", "ibm,emac-440epx", "ibm,emac4";
259 interrupt-parent = <&EMAC0>;
255 has-mdio;
256 };
257
258 EMAC0: ethernet@ef600e00 {
259 device_type = "network";
260 compatible = "ibm,emac-440grx", "ibm,emac-440epx", "ibm,emac4";
261 interrupt-parent = <&EMAC0>;
260 interrupts = <0 1>;
262 interrupts = <0x0 0x1>;
261 #interrupt-cells = <1>;
262 #address-cells = <0>;
263 #size-cells = <0>;
263 #interrupt-cells = <1>;
264 #address-cells = <0>;
265 #size-cells = <0>;
264 interrupt-map = </*Status*/ 0 &UIC0 18 4
265 /*Wake*/ 1 &UIC1 1d 4>;
266 reg = <ef600e00 70>;
266 interrupt-map = </*Status*/ 0x0 &UIC0 0x18 0x4
267 /*Wake*/ 0x1 &UIC1 0x1d 0x4>;
268 reg = <0xef600e00 0x00000070>;
267 local-mac-address = [000000000000];
268 mal-device = <&MAL0>;
269 mal-tx-channel = <0>;
270 mal-rx-channel = <0>;
271 cell-index = <0>;
269 local-mac-address = [000000000000];
270 mal-device = <&MAL0>;
271 mal-tx-channel = <0>;
272 mal-rx-channel = <0>;
273 cell-index = <0>;
272 max-frame-size = <2328>;
273 rx-fifo-size = <1000>;
274 tx-fifo-size = <800>;
274 max-frame-size = <9000>;
275 rx-fifo-size = <4096>;
276 tx-fifo-size = <2048>;
275 phy-mode = "rgmii";
277 phy-mode = "rgmii";
276 phy-map = <00000000>;
278 phy-map = <0x00000000>;
277 zmii-device = <&ZMII0>;
278 zmii-channel = <0>;
279 rgmii-device = <&RGMII0>;
280 rgmii-channel = <0>;
281 has-inverted-stacr-oc;
282 has-new-stacr-staopc;
283 };
284
285 EMAC1: ethernet@ef600f00 {
286 device_type = "network";
287 compatible = "ibm,emac-440grx", "ibm,emac-440epx", "ibm,emac4";
288 interrupt-parent = <&EMAC1>;
279 zmii-device = <&ZMII0>;
280 zmii-channel = <0>;
281 rgmii-device = <&RGMII0>;
282 rgmii-channel = <0>;
283 has-inverted-stacr-oc;
284 has-new-stacr-staopc;
285 };
286
287 EMAC1: ethernet@ef600f00 {
288 device_type = "network";
289 compatible = "ibm,emac-440grx", "ibm,emac-440epx", "ibm,emac4";
290 interrupt-parent = <&EMAC1>;
289 interrupts = <0 1>;
291 interrupts = <0x0 0x1>;
290 #interrupt-cells = <1>;
291 #address-cells = <0>;
292 #size-cells = <0>;
292 #interrupt-cells = <1>;
293 #address-cells = <0>;
294 #size-cells = <0>;
293 interrupt-map = </*Status*/ 0 &UIC0 19 4
294 /*Wake*/ 1 &UIC1 1f 4>;
295 reg = <ef600f00 70>;
295 interrupt-map = </*Status*/ 0x0 &UIC0 0x19 0x4
296 /*Wake*/ 0x1 &UIC1 0x1f 0x4>;
297 reg = <0xef600f00 0x00000070>;
296 local-mac-address = [000000000000];
297 mal-device = <&MAL0>;
298 mal-tx-channel = <1>;
299 mal-rx-channel = <1>;
300 cell-index = <1>;
298 local-mac-address = [000000000000];
299 mal-device = <&MAL0>;
300 mal-tx-channel = <1>;
301 mal-rx-channel = <1>;
302 cell-index = <1>;
301 max-frame-size = <2328>;
302 rx-fifo-size = <1000>;
303 tx-fifo-size = <800>;
303 max-frame-size = <9000>;
304 rx-fifo-size = <4096>;
305 tx-fifo-size = <2048>;
304 phy-mode = "rgmii";
306 phy-mode = "rgmii";
305 phy-map = <00000000>;
307 phy-map = <0x00000000>;
306 zmii-device = <&ZMII0>;
307 zmii-channel = <1>;
308 rgmii-device = <&RGMII0>;
309 rgmii-channel = <1>;
310 has-inverted-stacr-oc;
311 has-new-stacr-staopc;
312 };
313 };
314
315 PCI0: pci@1ec000000 {
316 device_type = "pci";
317 #interrupt-cells = <1>;
318 #size-cells = <2>;
319 #address-cells = <3>;
320 compatible = "ibm,plb440grx-pci", "ibm,plb-pci";
321 primary;
308 zmii-device = <&ZMII0>;
309 zmii-channel = <1>;
310 rgmii-device = <&RGMII0>;
311 rgmii-channel = <1>;
312 has-inverted-stacr-oc;
313 has-new-stacr-staopc;
314 };
315 };
316
317 PCI0: pci@1ec000000 {
318 device_type = "pci";
319 #interrupt-cells = <1>;
320 #size-cells = <2>;
321 #address-cells = <3>;
322 compatible = "ibm,plb440grx-pci", "ibm,plb-pci";
323 primary;
322 reg = <1 eec00000 8 /* Config space access */
323 1 eed00000 4 /* IACK */
324 1 eed00000 4 /* Special cycle */
325 1 ef400000 40>; /* Internal registers */
324 reg = <0x00000001 0xeec00000 0x00000008 /* Config space access */
325 0x00000001 0xeed00000 0x00000004 /* IACK */
326 0x00000001 0xeed00000 0x00000004 /* Special cycle */
327 0x00000001 0xef400000 0x00000040>; /* Internal registers */
326
327 /* Outbound ranges, one memory and one IO,
328 * later cannot be changed. Chip supports a second
329 * IO range but we don't use it for now
330 */
328
329 /* Outbound ranges, one memory and one IO,
330 * later cannot be changed. Chip supports a second
331 * IO range but we don't use it for now
332 */
331 ranges = <02000000 0 80000000 1 80000000 0 10000000
332 01000000 0 00000000 1 e8000000 0 00100000>;
333 ranges = <0x02000000 0x00000000 0x80000000 0x00000001 0x80000000 0x00000000 0x10000000
334 0x01000000 0x00000000 0x00000000 0x00000001 0xe8000000 0x00000000 0x00100000>;
333
334 /* Inbound 2GB range starting at 0 */
335
336 /* Inbound 2GB range starting at 0 */
335 dma-ranges = <42000000 0 0 0 0 0 80000000>;
337 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
336
337 /* All PCI interrupts are routed to IRQ 67 */
338
339 /* All PCI interrupts are routed to IRQ 67 */
338 interrupt-map-mask = <0000 0 0 0>;
339 interrupt-map = < 0000 0 0 0 &UIC2 3 8 >;
340 interrupt-map-mask = <0x0 0x0 0x0 0x0>;
341 interrupt-map = < 0x0 0x0 0x0 0x0 &UIC2 0x3 0x8 >;
340 };
341 };
342
343 chosen {
344 linux,stdout-path = "/plb/opb/serial@ef600300";
345 bootargs = "console=ttyS0,115200";
346 };
347};
342 };
343 };
344
345 chosen {
346 linux,stdout-path = "/plb/opb/serial@ef600300";
347 bootargs = "console=ttyS0,115200";
348 };
349};