ps3.dts (39fe5434cb9de5da40510028b17b96bc4eb312b3) ps3.dts (71f349799b34c8b6ce3df42126b4de6cfa16456d)
1/*
2 * PS3 Game Console device tree.
3 *
4 * Copyright (C) 2007 Sony Computer Entertainment Inc.
5 * Copyright 2007 Sony Corp.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by

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13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
1/*
2 * PS3 Game Console device tree.
3 *
4 * Copyright (C) 2007 Sony Computer Entertainment Inc.
5 * Copyright 2007 Sony Corp.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by

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13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21/dts-v1/;
22
21/ {
22 model = "SonyPS3";
23 compatible = "sony,ps3";
24 #size-cells = <2>;
25 #address-cells = <2>;
26
27 chosen {
28 };
29
30 /*
31 * We'll get the size of the bootmem block from lv1 after startup,
32 * so we'll put a null entry here.
33 */
34
35 memory {
36 device_type = "memory";
23/ {
24 model = "SonyPS3";
25 compatible = "sony,ps3";
26 #size-cells = <2>;
27 #address-cells = <2>;
28
29 chosen {
30 };
31
32 /*
33 * We'll get the size of the bootmem block from lv1 after startup,
34 * so we'll put a null entry here.
35 */
36
37 memory {
38 device_type = "memory";
37 reg = <0 0 0 0>;
39 reg = <0x00000000 0x00000000 0x00000000 0x00000000>;
38 };
39
40 /*
41 * The boot cpu is always zero for PS3.
42 *
43 * dtc expects a clock-frequency and timebase-frequency entries, so
44 * we'll put a null entries here. These will be initialized after
45 * startup with data from lv1.

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50 */
51
52 cpus {
53 #size-cells = <0>;
54 #address-cells = <1>;
55
56 cpu@0 {
57 device_type = "cpu";
40 };
41
42 /*
43 * The boot cpu is always zero for PS3.
44 *
45 * dtc expects a clock-frequency and timebase-frequency entries, so
46 * we'll put a null entries here. These will be initialized after
47 * startup with data from lv1.

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52 */
53
54 cpus {
55 #size-cells = <0>;
56 #address-cells = <1>;
57
58 cpu@0 {
59 device_type = "cpu";
58 reg = <0>;
59 ibm,ppc-interrupt-server#s = <0 1>;
60 reg = <0x00000000>;
61 ibm,ppc-interrupt-server#s = <0x0 0x1>;
60 clock-frequency = <0>;
61 timebase-frequency = <0>;
62 clock-frequency = <0>;
63 timebase-frequency = <0>;
62 i-cache-size = <8000>;
63 d-cache-size = <8000>;
64 i-cache-line-size = <80>;
65 d-cache-line-size = <80>;
64 i-cache-size = <32768>;
65 d-cache-size = <32768>;
66 i-cache-line-size = <128>;
67 d-cache-line-size = <128>;
66 };
67 };
68};
68 };
69 };
70};