icon.dts (c1144d29f405ce1f4e6ede6482beb3d0d09750c6) icon.dts (86bc917d2ac117ec922dbf8ed92ca989bf333281)
1/*
2 * Device Tree Source for Mosaix Technologies, Inc. ICON board
3 *
4 * Copyright 2010 DENX Software Engineering, Stefan Roese <sr@denx.de>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without
8 * any warranty of any kind, whether express or implied.

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310 /* This drives busses 0 to 0xf */
311 bus-range = <0x0 0xf>;
312
313 /* PCI-X interrupt (SM502) is routed to extIRQ10 (UIC1, 19) */
314 interrupt-map-mask = <0x0 0x0 0x0 0x0>;
315 interrupt-map = <0x0 0x0 0x0 0x0 &UIC1 19 0x8>;
316 };
317
1/*
2 * Device Tree Source for Mosaix Technologies, Inc. ICON board
3 *
4 * Copyright 2010 DENX Software Engineering, Stefan Roese <sr@denx.de>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without
8 * any warranty of any kind, whether express or implied.

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310 /* This drives busses 0 to 0xf */
311 bus-range = <0x0 0xf>;
312
313 /* PCI-X interrupt (SM502) is routed to extIRQ10 (UIC1, 19) */
314 interrupt-map-mask = <0x0 0x0 0x0 0x0>;
315 interrupt-map = <0x0 0x0 0x0 0x0 &UIC1 19 0x8>;
316 };
317
318 PCIE0: pciex@d00000000 {
318 PCIE0: pcie@d00000000 {
319 device_type = "pci";
320 #interrupt-cells = <1>;
321 #size-cells = <2>;
322 #address-cells = <3>;
323 compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex";
324 primary;
325 port = <0x0>; /* port number */
326 reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */

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351 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
352 interrupt-map = <
353 0x0 0x0 0x0 0x1 &UIC3 0x0 0x4 /* swizzled int A */
354 0x0 0x0 0x0 0x2 &UIC3 0x1 0x4 /* swizzled int B */
355 0x0 0x0 0x0 0x3 &UIC3 0x2 0x4 /* swizzled int C */
356 0x0 0x0 0x0 0x4 &UIC3 0x3 0x4 /* swizzled int D */>;
357 };
358
319 device_type = "pci";
320 #interrupt-cells = <1>;
321 #size-cells = <2>;
322 #address-cells = <3>;
323 compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex";
324 primary;
325 port = <0x0>; /* port number */
326 reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */

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351 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
352 interrupt-map = <
353 0x0 0x0 0x0 0x1 &UIC3 0x0 0x4 /* swizzled int A */
354 0x0 0x0 0x0 0x2 &UIC3 0x1 0x4 /* swizzled int B */
355 0x0 0x0 0x0 0x3 &UIC3 0x2 0x4 /* swizzled int C */
356 0x0 0x0 0x0 0x4 &UIC3 0x3 0x4 /* swizzled int D */>;
357 };
358
359 PCIE1: pciex@d20000000 {
359 PCIE1: pcie@d20000000 {
360 device_type = "pci";
361 #interrupt-cells = <1>;
362 #size-cells = <2>;
363 #address-cells = <3>;
364 compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex";
365 primary;
366 port = <0x1>; /* port number */
367 reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */

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360 device_type = "pci";
361 #interrupt-cells = <1>;
362 #size-cells = <2>;
363 #address-cells = <3>;
364 compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex";
365 primary;
366 port = <0x1>; /* port number */
367 reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */

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