glacier.dts (7022b15e2a9f878fd5184586064c63352c3dd225) glacier.dts (71f349799b34c8b6ce3df42126b4de6cfa16456d)
1/*
2 * Device Tree Source for AMCC Glacier (460GT)
3 *
4 * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without
8 * any warranty of any kind, whether express or implied.
9 */
10
1/*
2 * Device Tree Source for AMCC Glacier (460GT)
3 *
4 * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without
8 * any warranty of any kind, whether express or implied.
9 */
10
11/dts-v1/;
12
11/ {
12 #address-cells = <2>;
13 #size-cells = <1>;
14 model = "amcc,glacier";
15 compatible = "amcc,glacier", "amcc,canyonlands";
13/ {
14 #address-cells = <2>;
15 #size-cells = <1>;
16 model = "amcc,glacier";
17 compatible = "amcc,glacier", "amcc,canyonlands";
16 dcr-parent = <&/cpus/cpu@0>;
18 dcr-parent = <&{/cpus/cpu@0}>;
17
18 aliases {
19 ethernet0 = &EMAC0;
20 ethernet1 = &EMAC1;
21 ethernet2 = &EMAC2;
22 ethernet3 = &EMAC3;
23 serial0 = &UART0;
24 serial1 = &UART1;
25 };
26
27 cpus {
28 #address-cells = <1>;
29 #size-cells = <0>;
30
31 cpu@0 {
32 device_type = "cpu";
33 model = "PowerPC,460GT";
19
20 aliases {
21 ethernet0 = &EMAC0;
22 ethernet1 = &EMAC1;
23 ethernet2 = &EMAC2;
24 ethernet3 = &EMAC3;
25 serial0 = &UART0;
26 serial1 = &UART1;
27 };
28
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 cpu@0 {
34 device_type = "cpu";
35 model = "PowerPC,460GT";
34 reg = <0>;
36 reg = <0x00000000>;
35 clock-frequency = <0>; /* Filled in by U-Boot */
36 timebase-frequency = <0>; /* Filled in by U-Boot */
37 clock-frequency = <0>; /* Filled in by U-Boot */
38 timebase-frequency = <0>; /* Filled in by U-Boot */
37 i-cache-line-size = <20>;
38 d-cache-line-size = <20>;
39 i-cache-size = <8000>;
40 d-cache-size = <8000>;
39 i-cache-line-size = <32>;
40 d-cache-line-size = <32>;
41 i-cache-size = <32768>;
42 d-cache-size = <32768>;
41 dcr-controller;
42 dcr-access-method = "native";
43 };
44 };
45
46 memory {
47 device_type = "memory";
43 dcr-controller;
44 dcr-access-method = "native";
45 };
46 };
47
48 memory {
49 device_type = "memory";
48 reg = <0 0 0>; /* Filled in by U-Boot */
50 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
49 };
50
51 UIC0: interrupt-controller0 {
52 compatible = "ibm,uic-460gt","ibm,uic";
53 interrupt-controller;
54 cell-index = <0>;
51 };
52
53 UIC0: interrupt-controller0 {
54 compatible = "ibm,uic-460gt","ibm,uic";
55 interrupt-controller;
56 cell-index = <0>;
55 dcr-reg = <0c0 009>;
57 dcr-reg = <0x0c0 0x009>;
56 #address-cells = <0>;
57 #size-cells = <0>;
58 #interrupt-cells = <2>;
59 };
60
61 UIC1: interrupt-controller1 {
62 compatible = "ibm,uic-460gt","ibm,uic";
63 interrupt-controller;
64 cell-index = <1>;
58 #address-cells = <0>;
59 #size-cells = <0>;
60 #interrupt-cells = <2>;
61 };
62
63 UIC1: interrupt-controller1 {
64 compatible = "ibm,uic-460gt","ibm,uic";
65 interrupt-controller;
66 cell-index = <1>;
65 dcr-reg = <0d0 009>;
67 dcr-reg = <0x0d0 0x009>;
66 #address-cells = <0>;
67 #size-cells = <0>;
68 #interrupt-cells = <2>;
68 #address-cells = <0>;
69 #size-cells = <0>;
70 #interrupt-cells = <2>;
69 interrupts = <1e 4 1f 4>; /* cascade */
71 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
70 interrupt-parent = <&UIC0>;
71 };
72
73 UIC2: interrupt-controller2 {
74 compatible = "ibm,uic-460gt","ibm,uic";
75 interrupt-controller;
76 cell-index = <2>;
72 interrupt-parent = <&UIC0>;
73 };
74
75 UIC2: interrupt-controller2 {
76 compatible = "ibm,uic-460gt","ibm,uic";
77 interrupt-controller;
78 cell-index = <2>;
77 dcr-reg = <0e0 009>;
79 dcr-reg = <0x0e0 0x009>;
78 #address-cells = <0>;
79 #size-cells = <0>;
80 #interrupt-cells = <2>;
80 #address-cells = <0>;
81 #size-cells = <0>;
82 #interrupt-cells = <2>;
81 interrupts = <a 4 b 4>; /* cascade */
83 interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
82 interrupt-parent = <&UIC0>;
83 };
84
85 UIC3: interrupt-controller3 {
86 compatible = "ibm,uic-460gt","ibm,uic";
87 interrupt-controller;
88 cell-index = <3>;
84 interrupt-parent = <&UIC0>;
85 };
86
87 UIC3: interrupt-controller3 {
88 compatible = "ibm,uic-460gt","ibm,uic";
89 interrupt-controller;
90 cell-index = <3>;
89 dcr-reg = <0f0 009>;
91 dcr-reg = <0x0f0 0x009>;
90 #address-cells = <0>;
91 #size-cells = <0>;
92 #interrupt-cells = <2>;
92 #address-cells = <0>;
93 #size-cells = <0>;
94 #interrupt-cells = <2>;
93 interrupts = <10 4 11 4>; /* cascade */
95 interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
94 interrupt-parent = <&UIC0>;
95 };
96
97 SDR0: sdr {
98 compatible = "ibm,sdr-460gt";
96 interrupt-parent = <&UIC0>;
97 };
98
99 SDR0: sdr {
100 compatible = "ibm,sdr-460gt";
99 dcr-reg = <00e 002>;
101 dcr-reg = <0x00e 0x002>;
100 };
101
102 CPR0: cpr {
103 compatible = "ibm,cpr-460gt";
102 };
103
104 CPR0: cpr {
105 compatible = "ibm,cpr-460gt";
104 dcr-reg = <00c 002>;
106 dcr-reg = <0x00c 0x002>;
105 };
106
107 plb {
108 compatible = "ibm,plb-460gt", "ibm,plb4";
109 #address-cells = <2>;
110 #size-cells = <1>;
111 ranges;
112 clock-frequency = <0>; /* Filled in by U-Boot */
113
114 SDRAM0: sdram {
115 compatible = "ibm,sdram-460gt", "ibm,sdram-405gp";
107 };
108
109 plb {
110 compatible = "ibm,plb-460gt", "ibm,plb4";
111 #address-cells = <2>;
112 #size-cells = <1>;
113 ranges;
114 clock-frequency = <0>; /* Filled in by U-Boot */
115
116 SDRAM0: sdram {
117 compatible = "ibm,sdram-460gt", "ibm,sdram-405gp";
116 dcr-reg = <010 2>;
118 dcr-reg = <0x010 0x002>;
117 };
118
119 MAL0: mcmal {
120 compatible = "ibm,mcmal-460gt", "ibm,mcmal2";
119 };
120
121 MAL0: mcmal {
122 compatible = "ibm,mcmal-460gt", "ibm,mcmal2";
121 dcr-reg = <180 62>;
123 dcr-reg = <0x180 0x062>;
122 num-tx-chans = <4>;
124 num-tx-chans = <4>;
123 num-rx-chans = <20>;
125 num-rx-chans = <32>;
124 #address-cells = <0>;
125 #size-cells = <0>;
126 interrupt-parent = <&UIC2>;
126 #address-cells = <0>;
127 #size-cells = <0>;
128 interrupt-parent = <&UIC2>;
127 interrupts = < /*TXEOB*/ 6 4
128 /*RXEOB*/ 7 4
129 /*SERR*/ 3 4
130 /*TXDE*/ 4 4
131 /*RXDE*/ 5 4>;
132 desc-base-addr-high = <8>;
129 interrupts = < /*TXEOB*/ 0x6 0x4
130 /*RXEOB*/ 0x7 0x4
131 /*SERR*/ 0x3 0x4
132 /*TXDE*/ 0x4 0x4
133 /*RXDE*/ 0x5 0x4>;
134 desc-base-addr-high = <0x8>;
133 };
134
135 POB0: opb {
136 compatible = "ibm,opb-460gt", "ibm,opb";
137 #address-cells = <1>;
138 #size-cells = <1>;
135 };
136
137 POB0: opb {
138 compatible = "ibm,opb-460gt", "ibm,opb";
139 #address-cells = <1>;
140 #size-cells = <1>;
139 ranges = <b0000000 4 b0000000 50000000>;
141 ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
140 clock-frequency = <0>; /* Filled in by U-Boot */
141
142 EBC0: ebc {
143 compatible = "ibm,ebc-460gt", "ibm,ebc";
142 clock-frequency = <0>; /* Filled in by U-Boot */
143
144 EBC0: ebc {
145 compatible = "ibm,ebc-460gt", "ibm,ebc";
144 dcr-reg = <012 2>;
146 dcr-reg = <0x012 0x002>;
145 #address-cells = <2>;
146 #size-cells = <1>;
147 clock-frequency = <0>; /* Filled in by U-Boot */
148 /* ranges property is supplied by U-Boot */
147 #address-cells = <2>;
148 #size-cells = <1>;
149 clock-frequency = <0>; /* Filled in by U-Boot */
150 /* ranges property is supplied by U-Boot */
149 interrupts = <6 4>;
151 interrupts = <0x6 0x4>;
150 interrupt-parent = <&UIC1>;
151
152 nor_flash@0,0 {
153 compatible = "amd,s29gl512n", "cfi-flash";
154 bank-width = <2>;
152 interrupt-parent = <&UIC1>;
153
154 nor_flash@0,0 {
155 compatible = "amd,s29gl512n", "cfi-flash";
156 bank-width = <2>;
155 reg = <0 000000 4000000>;
157 reg = <0x00000000 0x00000000 0x04000000>;
156 #address-cells = <1>;
157 #size-cells = <1>;
158 partition@0 {
159 label = "kernel";
158 #address-cells = <1>;
159 #size-cells = <1>;
160 partition@0 {
161 label = "kernel";
160 reg = <0 1e0000>;
162 reg = <0x00000000 0x001e0000>;
161 };
162 partition@1e0000 {
163 label = "dtb";
163 };
164 partition@1e0000 {
165 label = "dtb";
164 reg = <1e0000 20000>;
166 reg = <0x001e0000 0x00020000>;
165 };
166 partition@200000 {
167 label = "ramdisk";
167 };
168 partition@200000 {
169 label = "ramdisk";
168 reg = <200000 1400000>;
170 reg = <0x00200000 0x01400000>;
169 };
170 partition@1600000 {
171 label = "jffs2";
171 };
172 partition@1600000 {
173 label = "jffs2";
172 reg = <1600000 400000>;
174 reg = <0x01600000 0x00400000>;
173 };
174 partition@1a00000 {
175 label = "user";
175 };
176 partition@1a00000 {
177 label = "user";
176 reg = <1a00000 2560000>;
178 reg = <0x01a00000 0x02560000>;
177 };
178 partition@3f60000 {
179 label = "env";
179 };
180 partition@3f60000 {
181 label = "env";
180 reg = <3f60000 40000>;
182 reg = <0x03f60000 0x00040000>;
181 };
182 partition@3fa0000 {
183 label = "u-boot";
183 };
184 partition@3fa0000 {
185 label = "u-boot";
184 reg = <3fa0000 60000>;
186 reg = <0x03fa0000 0x00060000>;
185 };
186 };
187 };
188
189 UART0: serial@ef600300 {
190 device_type = "serial";
191 compatible = "ns16550";
187 };
188 };
189 };
190
191 UART0: serial@ef600300 {
192 device_type = "serial";
193 compatible = "ns16550";
192 reg = <ef600300 8>;
193 virtual-reg = <ef600300>;
194 reg = <0xef600300 0x00000008>;
195 virtual-reg = <0xef600300>;
194 clock-frequency = <0>; /* Filled in by U-Boot */
195 current-speed = <0>; /* Filled in by U-Boot */
196 interrupt-parent = <&UIC1>;
196 clock-frequency = <0>; /* Filled in by U-Boot */
197 current-speed = <0>; /* Filled in by U-Boot */
198 interrupt-parent = <&UIC1>;
197 interrupts = <1 4>;
199 interrupts = <0x1 0x4>;
198 };
199
200 UART1: serial@ef600400 {
201 device_type = "serial";
202 compatible = "ns16550";
200 };
201
202 UART1: serial@ef600400 {
203 device_type = "serial";
204 compatible = "ns16550";
203 reg = <ef600400 8>;
204 virtual-reg = <ef600400>;
205 reg = <0xef600400 0x00000008>;
206 virtual-reg = <0xef600400>;
205 clock-frequency = <0>; /* Filled in by U-Boot */
206 current-speed = <0>; /* Filled in by U-Boot */
207 interrupt-parent = <&UIC0>;
207 clock-frequency = <0>; /* Filled in by U-Boot */
208 current-speed = <0>; /* Filled in by U-Boot */
209 interrupt-parent = <&UIC0>;
208 interrupts = <1 4>;
210 interrupts = <0x1 0x4>;
209 };
210
211 UART2: serial@ef600500 {
212 device_type = "serial";
213 compatible = "ns16550";
211 };
212
213 UART2: serial@ef600500 {
214 device_type = "serial";
215 compatible = "ns16550";
214 reg = <ef600500 8>;
215 virtual-reg = <ef600500>;
216 reg = <0xef600500 0x00000008>;
217 virtual-reg = <0xef600500>;
216 clock-frequency = <0>; /* Filled in by U-Boot */
217 current-speed = <0>; /* Filled in by U-Boot */
218 interrupt-parent = <&UIC1>;
218 clock-frequency = <0>; /* Filled in by U-Boot */
219 current-speed = <0>; /* Filled in by U-Boot */
220 interrupt-parent = <&UIC1>;
219 interrupts = <1d 4>;
221 interrupts = <0x1d 0x4>;
220 };
221
222 UART3: serial@ef600600 {
223 device_type = "serial";
224 compatible = "ns16550";
222 };
223
224 UART3: serial@ef600600 {
225 device_type = "serial";
226 compatible = "ns16550";
225 reg = <ef600600 8>;
226 virtual-reg = <ef600600>;
227 reg = <0xef600600 0x00000008>;
228 virtual-reg = <0xef600600>;
227 clock-frequency = <0>; /* Filled in by U-Boot */
228 current-speed = <0>; /* Filled in by U-Boot */
229 interrupt-parent = <&UIC1>;
229 clock-frequency = <0>; /* Filled in by U-Boot */
230 current-speed = <0>; /* Filled in by U-Boot */
231 interrupt-parent = <&UIC1>;
230 interrupts = <1e 4>;
232 interrupts = <0x1e 0x4>;
231 };
232
233 IIC0: i2c@ef600700 {
234 compatible = "ibm,iic-460gt", "ibm,iic";
233 };
234
235 IIC0: i2c@ef600700 {
236 compatible = "ibm,iic-460gt", "ibm,iic";
235 reg = <ef600700 14>;
237 reg = <0xef600700 0x00000014>;
236 interrupt-parent = <&UIC0>;
238 interrupt-parent = <&UIC0>;
237 interrupts = <2 4>;
239 interrupts = <0x2 0x4>;
238 };
239
240 IIC1: i2c@ef600800 {
241 compatible = "ibm,iic-460gt", "ibm,iic";
240 };
241
242 IIC1: i2c@ef600800 {
243 compatible = "ibm,iic-460gt", "ibm,iic";
242 reg = <ef600800 14>;
244 reg = <0xef600800 0x00000014>;
243 interrupt-parent = <&UIC0>;
245 interrupt-parent = <&UIC0>;
244 interrupts = <3 4>;
246 interrupts = <0x3 0x4>;
245 };
246
247 ZMII0: emac-zmii@ef600d00 {
248 compatible = "ibm,zmii-460gt", "ibm,zmii";
247 };
248
249 ZMII0: emac-zmii@ef600d00 {
250 compatible = "ibm,zmii-460gt", "ibm,zmii";
249 reg = <ef600d00 c>;
251 reg = <0xef600d00 0x0000000c>;
250 };
251
252 RGMII0: emac-rgmii@ef601500 {
253 compatible = "ibm,rgmii-460gt", "ibm,rgmii";
252 };
253
254 RGMII0: emac-rgmii@ef601500 {
255 compatible = "ibm,rgmii-460gt", "ibm,rgmii";
254 reg = <ef601500 8>;
256 reg = <0xef601500 0x00000008>;
255 has-mdio;
256 };
257
258 RGMII1: emac-rgmii@ef601600 {
259 compatible = "ibm,rgmii-460gt", "ibm,rgmii";
257 has-mdio;
258 };
259
260 RGMII1: emac-rgmii@ef601600 {
261 compatible = "ibm,rgmii-460gt", "ibm,rgmii";
260 reg = <ef601600 8>;
262 reg = <0xef601600 0x00000008>;
261 has-mdio;
262 };
263
264 TAH0: emac-tah@ef601350 {
265 compatible = "ibm,tah-460gt", "ibm,tah";
263 has-mdio;
264 };
265
266 TAH0: emac-tah@ef601350 {
267 compatible = "ibm,tah-460gt", "ibm,tah";
266 reg = <ef601350 30>;
268 reg = <0xef601350 0x00000030>;
267 };
268
269 TAH1: emac-tah@ef601450 {
270 compatible = "ibm,tah-460gt", "ibm,tah";
269 };
270
271 TAH1: emac-tah@ef601450 {
272 compatible = "ibm,tah-460gt", "ibm,tah";
271 reg = <ef601450 30>;
273 reg = <0xef601450 0x00000030>;
272 };
273
274 EMAC0: ethernet@ef600e00 {
275 device_type = "network";
276 compatible = "ibm,emac-460gt", "ibm,emac4";
277 interrupt-parent = <&EMAC0>;
274 };
275
276 EMAC0: ethernet@ef600e00 {
277 device_type = "network";
278 compatible = "ibm,emac-460gt", "ibm,emac4";
279 interrupt-parent = <&EMAC0>;
278 interrupts = <0 1>;
280 interrupts = <0x0 0x1>;
279 #interrupt-cells = <1>;
280 #address-cells = <0>;
281 #size-cells = <0>;
281 #interrupt-cells = <1>;
282 #address-cells = <0>;
283 #size-cells = <0>;
282 interrupt-map = </*Status*/ 0 &UIC2 10 4
283 /*Wake*/ 1 &UIC2 14 4>;
284 reg = <ef600e00 70>;
284 interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4
285 /*Wake*/ 0x1 &UIC2 0x14 0x4>;
286 reg = <0xef600e00 0x00000070>;
285 local-mac-address = [000000000000]; /* Filled in by U-Boot */
286 mal-device = <&MAL0>;
287 mal-tx-channel = <0>;
288 mal-rx-channel = <0>;
289 cell-index = <0>;
287 local-mac-address = [000000000000]; /* Filled in by U-Boot */
288 mal-device = <&MAL0>;
289 mal-tx-channel = <0>;
290 mal-rx-channel = <0>;
291 cell-index = <0>;
290 max-frame-size = <2328>;
291 rx-fifo-size = <1000>;
292 tx-fifo-size = <800>;
292 max-frame-size = <9000>;
293 rx-fifo-size = <4096>;
294 tx-fifo-size = <2048>;
293 phy-mode = "rgmii";
295 phy-mode = "rgmii";
294 phy-map = <00000000>;
296 phy-map = <0x00000000>;
295 rgmii-device = <&RGMII0>;
296 rgmii-channel = <0>;
297 tah-device = <&TAH0>;
298 tah-channel = <0>;
299 has-inverted-stacr-oc;
300 has-new-stacr-staopc;
301 };
302
303 EMAC1: ethernet@ef600f00 {
304 device_type = "network";
305 compatible = "ibm,emac-460gt", "ibm,emac4";
306 interrupt-parent = <&EMAC1>;
297 rgmii-device = <&RGMII0>;
298 rgmii-channel = <0>;
299 tah-device = <&TAH0>;
300 tah-channel = <0>;
301 has-inverted-stacr-oc;
302 has-new-stacr-staopc;
303 };
304
305 EMAC1: ethernet@ef600f00 {
306 device_type = "network";
307 compatible = "ibm,emac-460gt", "ibm,emac4";
308 interrupt-parent = <&EMAC1>;
307 interrupts = <0 1>;
309 interrupts = <0x0 0x1>;
308 #interrupt-cells = <1>;
309 #address-cells = <0>;
310 #size-cells = <0>;
310 #interrupt-cells = <1>;
311 #address-cells = <0>;
312 #size-cells = <0>;
311 interrupt-map = </*Status*/ 0 &UIC2 11 4
312 /*Wake*/ 1 &UIC2 15 4>;
313 reg = <ef600f00 70>;
313 interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4
314 /*Wake*/ 0x1 &UIC2 0x15 0x4>;
315 reg = <0xef600f00 0x00000070>;
314 local-mac-address = [000000000000]; /* Filled in by U-Boot */
315 mal-device = <&MAL0>;
316 mal-tx-channel = <1>;
317 mal-rx-channel = <8>;
318 cell-index = <1>;
316 local-mac-address = [000000000000]; /* Filled in by U-Boot */
317 mal-device = <&MAL0>;
318 mal-tx-channel = <1>;
319 mal-rx-channel = <8>;
320 cell-index = <1>;
319 max-frame-size = <2328>;
320 rx-fifo-size = <1000>;
321 tx-fifo-size = <800>;
321 max-frame-size = <9000>;
322 rx-fifo-size = <4096>;
323 tx-fifo-size = <2048>;
322 phy-mode = "rgmii";
324 phy-mode = "rgmii";
323 phy-map = <00000000>;
325 phy-map = <0x00000000>;
324 rgmii-device = <&RGMII0>;
325 rgmii-channel = <1>;
326 tah-device = <&TAH1>;
327 tah-channel = <1>;
328 has-inverted-stacr-oc;
329 has-new-stacr-staopc;
330 mdio-device = <&EMAC0>;
331 };
332
333 EMAC2: ethernet@ef601100 {
334 device_type = "network";
335 compatible = "ibm,emac-460gt", "ibm,emac4";
336 interrupt-parent = <&EMAC2>;
326 rgmii-device = <&RGMII0>;
327 rgmii-channel = <1>;
328 tah-device = <&TAH1>;
329 tah-channel = <1>;
330 has-inverted-stacr-oc;
331 has-new-stacr-staopc;
332 mdio-device = <&EMAC0>;
333 };
334
335 EMAC2: ethernet@ef601100 {
336 device_type = "network";
337 compatible = "ibm,emac-460gt", "ibm,emac4";
338 interrupt-parent = <&EMAC2>;
337 interrupts = <0 1>;
339 interrupts = <0x0 0x1>;
338 #interrupt-cells = <1>;
339 #address-cells = <0>;
340 #size-cells = <0>;
340 #interrupt-cells = <1>;
341 #address-cells = <0>;
342 #size-cells = <0>;
341 interrupt-map = </*Status*/ 0 &UIC2 12 4
342 /*Wake*/ 1 &UIC2 16 4>;
343 reg = <ef601100 70>;
343 interrupt-map = </*Status*/ 0x0 &UIC2 0x12 0x4
344 /*Wake*/ 0x1 &UIC2 0x16 0x4>;
345 reg = <0xef601100 0x00000070>;
344 local-mac-address = [000000000000]; /* Filled in by U-Boot */
345 mal-device = <&MAL0>;
346 mal-tx-channel = <2>;
346 local-mac-address = [000000000000]; /* Filled in by U-Boot */
347 mal-device = <&MAL0>;
348 mal-tx-channel = <2>;
347 mal-rx-channel = <10>;
349 mal-rx-channel = <16>;
348 cell-index = <2>;
350 cell-index = <2>;
349 max-frame-size = <2328>;
350 rx-fifo-size = <1000>;
351 tx-fifo-size = <800>;
351 max-frame-size = <9000>;
352 rx-fifo-size = <4096>;
353 tx-fifo-size = <2048>;
352 phy-mode = "rgmii";
354 phy-mode = "rgmii";
353 phy-map = <00000000>;
355 phy-map = <0x00000000>;
354 rgmii-device = <&RGMII1>;
355 rgmii-channel = <0>;
356 has-inverted-stacr-oc;
357 has-new-stacr-staopc;
358 mdio-device = <&EMAC0>;
359 };
360
361 EMAC3: ethernet@ef601200 {
362 device_type = "network";
363 compatible = "ibm,emac-460gt", "ibm,emac4";
364 interrupt-parent = <&EMAC3>;
356 rgmii-device = <&RGMII1>;
357 rgmii-channel = <0>;
358 has-inverted-stacr-oc;
359 has-new-stacr-staopc;
360 mdio-device = <&EMAC0>;
361 };
362
363 EMAC3: ethernet@ef601200 {
364 device_type = "network";
365 compatible = "ibm,emac-460gt", "ibm,emac4";
366 interrupt-parent = <&EMAC3>;
365 interrupts = <0 1>;
367 interrupts = <0x0 0x1>;
366 #interrupt-cells = <1>;
367 #address-cells = <0>;
368 #size-cells = <0>;
368 #interrupt-cells = <1>;
369 #address-cells = <0>;
370 #size-cells = <0>;
369 interrupt-map = </*Status*/ 0 &UIC2 13 4
370 /*Wake*/ 1 &UIC2 17 4>;
371 reg = <ef601200 70>;
371 interrupt-map = </*Status*/ 0x0 &UIC2 0x13 0x4
372 /*Wake*/ 0x1 &UIC2 0x17 0x4>;
373 reg = <0xef601200 0x00000070>;
372 local-mac-address = [000000000000]; /* Filled in by U-Boot */
373 mal-device = <&MAL0>;
374 mal-tx-channel = <3>;
374 local-mac-address = [000000000000]; /* Filled in by U-Boot */
375 mal-device = <&MAL0>;
376 mal-tx-channel = <3>;
375 mal-rx-channel = <18>;
377 mal-rx-channel = <24>;
376 cell-index = <3>;
378 cell-index = <3>;
377 max-frame-size = <2328>;
378 rx-fifo-size = <1000>;
379 tx-fifo-size = <800>;
379 max-frame-size = <9000>;
380 rx-fifo-size = <4096>;
381 tx-fifo-size = <2048>;
380 phy-mode = "rgmii";
382 phy-mode = "rgmii";
381 phy-map = <00000000>;
383 phy-map = <0x00000000>;
382 rgmii-device = <&RGMII1>;
383 rgmii-channel = <1>;
384 has-inverted-stacr-oc;
385 has-new-stacr-staopc;
386 mdio-device = <&EMAC0>;
387 };
388 };
389
390 PCIX0: pci@c0ec00000 {
391 device_type = "pci";
392 #interrupt-cells = <1>;
393 #size-cells = <2>;
394 #address-cells = <3>;
395 compatible = "ibm,plb-pcix-460gt", "ibm,plb-pcix";
396 primary;
397 large-inbound-windows;
398 enable-msi-hole;
384 rgmii-device = <&RGMII1>;
385 rgmii-channel = <1>;
386 has-inverted-stacr-oc;
387 has-new-stacr-staopc;
388 mdio-device = <&EMAC0>;
389 };
390 };
391
392 PCIX0: pci@c0ec00000 {
393 device_type = "pci";
394 #interrupt-cells = <1>;
395 #size-cells = <2>;
396 #address-cells = <3>;
397 compatible = "ibm,plb-pcix-460gt", "ibm,plb-pcix";
398 primary;
399 large-inbound-windows;
400 enable-msi-hole;
399 reg = <c 0ec00000 8 /* Config space access */
400 0 0 0 /* no IACK cycles */
401 c 0ed00000 4 /* Special cycles */
402 c 0ec80000 100 /* Internal registers */
403 c 0ec80100 fc>; /* Internal messaging registers */
401 reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */
402 0x00000000 0x00000000 0x00000000 /* no IACK cycles */
403 0x0000000c 0x0ed00000 0x00000004 /* Special cycles */
404 0x0000000c 0x0ec80000 0x00000100 /* Internal registers */
405 0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */
404
405 /* Outbound ranges, one memory and one IO,
406 * later cannot be changed
407 */
406
407 /* Outbound ranges, one memory and one IO,
408 * later cannot be changed
409 */
408 ranges = <02000000 0 80000000 0000000d 80000000 0 80000000
409 01000000 0 00000000 0000000c 08000000 0 00010000>;
410 ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000
411 0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>;
410
411 /* Inbound 2GB range starting at 0 */
412
413 /* Inbound 2GB range starting at 0 */
412 dma-ranges = <42000000 0 0 0 0 0 80000000>;
414 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
413
414 /* This drives busses 0 to 0x3f */
415
416 /* This drives busses 0 to 0x3f */
415 bus-range = <0 3f>;
417 bus-range = <0x0 0x3f>;
416
417 /* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */
418
419 /* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */
418 interrupt-map-mask = <0000 0 0 0>;
419 interrupt-map = < 0000 0 0 0 &UIC1 0 8 >;
420 interrupt-map-mask = <0x0 0x0 0x0 0x0>;
421 interrupt-map = < 0x0 0x0 0x0 0x0 &UIC1 0x0 0x8 >;
420 };
421
422 PCIE0: pciex@d00000000 {
423 device_type = "pci";
424 #interrupt-cells = <1>;
425 #size-cells = <2>;
426 #address-cells = <3>;
427 compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
428 primary;
422 };
423
424 PCIE0: pciex@d00000000 {
425 device_type = "pci";
426 #interrupt-cells = <1>;
427 #size-cells = <2>;
428 #address-cells = <3>;
429 compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
430 primary;
429 port = <0>; /* port number */
430 reg = <d 00000000 20000000 /* Config space access */
431 c 08010000 00001000>; /* Registers */
432 dcr-reg = <100 020>;
433 sdr-base = <300>;
431 port = <0x0>; /* port number */
432 reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */
433 0x0000000c 0x08010000 0x00001000>; /* Registers */
434 dcr-reg = <0x100 0x020>;
435 sdr-base = <0x300>;
434
435 /* Outbound ranges, one memory and one IO,
436 * later cannot be changed
437 */
436
437 /* Outbound ranges, one memory and one IO,
438 * later cannot be changed
439 */
438 ranges = <02000000 0 80000000 0000000e 00000000 0 80000000
439 01000000 0 00000000 0000000f 80000000 0 00010000>;
440 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
441 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
440
441 /* Inbound 2GB range starting at 0 */
442
443 /* Inbound 2GB range starting at 0 */
442 dma-ranges = <42000000 0 0 0 0 0 80000000>;
444 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
443
444 /* This drives busses 40 to 0x7f */
445
446 /* This drives busses 40 to 0x7f */
445 bus-range = <40 7f>;
447 bus-range = <0x40 0x7f>;
446
447 /* Legacy interrupts (note the weird polarity, the bridge seems
448 * to invert PCIe legacy interrupts).
449 * We are de-swizzling here because the numbers are actually for
450 * port of the root complex virtual P2P bridge. But I want
451 * to avoid putting a node for it in the tree, so the numbers
452 * below are basically de-swizzled numbers.
453 * The real slot is on idsel 0, so the swizzling is 1:1
454 */
448
449 /* Legacy interrupts (note the weird polarity, the bridge seems
450 * to invert PCIe legacy interrupts).
451 * We are de-swizzling here because the numbers are actually for
452 * port of the root complex virtual P2P bridge. But I want
453 * to avoid putting a node for it in the tree, so the numbers
454 * below are basically de-swizzled numbers.
455 * The real slot is on idsel 0, so the swizzling is 1:1
456 */
455 interrupt-map-mask = <0000 0 0 7>;
457 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
456 interrupt-map = <
458 interrupt-map = <
457 0000 0 0 1 &UIC3 c 4 /* swizzled int A */
458 0000 0 0 2 &UIC3 d 4 /* swizzled int B */
459 0000 0 0 3 &UIC3 e 4 /* swizzled int C */
460 0000 0 0 4 &UIC3 f 4 /* swizzled int D */>;
459 0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */
460 0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */
461 0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */
462 0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>;
461 };
462
463 PCIE1: pciex@d20000000 {
464 device_type = "pci";
465 #interrupt-cells = <1>;
466 #size-cells = <2>;
467 #address-cells = <3>;
468 compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
469 primary;
463 };
464
465 PCIE1: pciex@d20000000 {
466 device_type = "pci";
467 #interrupt-cells = <1>;
468 #size-cells = <2>;
469 #address-cells = <3>;
470 compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
471 primary;
470 port = <1>; /* port number */
471 reg = <d 20000000 20000000 /* Config space access */
472 c 08011000 00001000>; /* Registers */
473 dcr-reg = <120 020>;
474 sdr-base = <340>;
472 port = <0x1>; /* port number */
473 reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */
474 0x0000000c 0x08011000 0x00001000>; /* Registers */
475 dcr-reg = <0x120 0x020>;
476 sdr-base = <0x340>;
475
476 /* Outbound ranges, one memory and one IO,
477 * later cannot be changed
478 */
477
478 /* Outbound ranges, one memory and one IO,
479 * later cannot be changed
480 */
479 ranges = <02000000 0 80000000 0000000e 80000000 0 80000000
480 01000000 0 00000000 0000000f 80010000 0 00010000>;
481 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000
482 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>;
481
482 /* Inbound 2GB range starting at 0 */
483
484 /* Inbound 2GB range starting at 0 */
483 dma-ranges = <42000000 0 0 0 0 0 80000000>;
485 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
484
485 /* This drives busses 80 to 0xbf */
486
487 /* This drives busses 80 to 0xbf */
486 bus-range = <80 bf>;
488 bus-range = <0x80 0xbf>;
487
488 /* Legacy interrupts (note the weird polarity, the bridge seems
489 * to invert PCIe legacy interrupts).
490 * We are de-swizzling here because the numbers are actually for
491 * port of the root complex virtual P2P bridge. But I want
492 * to avoid putting a node for it in the tree, so the numbers
493 * below are basically de-swizzled numbers.
494 * The real slot is on idsel 0, so the swizzling is 1:1
495 */
489
490 /* Legacy interrupts (note the weird polarity, the bridge seems
491 * to invert PCIe legacy interrupts).
492 * We are de-swizzling here because the numbers are actually for
493 * port of the root complex virtual P2P bridge. But I want
494 * to avoid putting a node for it in the tree, so the numbers
495 * below are basically de-swizzled numbers.
496 * The real slot is on idsel 0, so the swizzling is 1:1
497 */
496 interrupt-map-mask = <0000 0 0 7>;
498 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
497 interrupt-map = <
499 interrupt-map = <
498 0000 0 0 1 &UIC3 10 4 /* swizzled int A */
499 0000 0 0 2 &UIC3 11 4 /* swizzled int B */
500 0000 0 0 3 &UIC3 12 4 /* swizzled int C */
501 0000 0 0 4 &UIC3 13 4 /* swizzled int D */>;
500 0x0 0x0 0x0 0x1 &UIC3 0x10 0x4 /* swizzled int A */
501 0x0 0x0 0x0 0x2 &UIC3 0x11 0x4 /* swizzled int B */
502 0x0 0x0 0x0 0x3 &UIC3 0x12 0x4 /* swizzled int C */
503 0x0 0x0 0x0 0x4 &UIC3 0x13 0x4 /* swizzled int D */>;
502 };
503 };
504};
504 };
505 };
506};