canyonlands.dts (8f987768eb99631374f4ab0bb19cd062baf1397d) canyonlands.dts (ee2ffd8bbb2170f9b52fc8ff4aebe9702e0de651)
1/*
2 * Device Tree Source for AMCC Canyonlands (460EX)
3 *
4 * Copyright 2008-2009 DENX Software Engineering, Stefan Roese <sr@denx.de>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without
8 * any warranty of any kind, whether express or implied.

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100 dcr-reg = <0x00e 0x002>;
101 };
102
103 CPR0: cpr {
104 compatible = "ibm,cpr-460ex";
105 dcr-reg = <0x00c 0x002>;
106 };
107
1/*
2 * Device Tree Source for AMCC Canyonlands (460EX)
3 *
4 * Copyright 2008-2009 DENX Software Engineering, Stefan Roese <sr@denx.de>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without
8 * any warranty of any kind, whether express or implied.

--- 91 unchanged lines hidden (view full) ---

100 dcr-reg = <0x00e 0x002>;
101 };
102
103 CPR0: cpr {
104 compatible = "ibm,cpr-460ex";
105 dcr-reg = <0x00c 0x002>;
106 };
107
108 CPM0: cpm {
109 compatible = "ibm,cpm";
110 dcr-access-method = "native";
111 dcr-reg = <0x160 0x003>;
112 unused-units = <0x00000100>;
113 idle-doze = <0x02000000>;
114 standby = <0xfeff791d>;
115 };
116
108 L2C0: l2c {
109 compatible = "ibm,l2-cache-460ex", "ibm,l2-cache";
110 dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */
111 0x030 0x008>; /* L2 cache DCR's */
112 cache-line-size = <32>; /* 32 bytes */
113 cache-size = <262144>; /* L2, 256K */
114 interrupt-parent = <&UIC1>;
115 interrupts = <11 1>;

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265 reg = <0xef600400 0x00000008>;
266 virtual-reg = <0xef600400>;
267 clock-frequency = <0>; /* Filled in by U-Boot */
268 current-speed = <0>; /* Filled in by U-Boot */
269 interrupt-parent = <&UIC0>;
270 interrupts = <0x1 0x4>;
271 };
272
117 L2C0: l2c {
118 compatible = "ibm,l2-cache-460ex", "ibm,l2-cache";
119 dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */
120 0x030 0x008>; /* L2 cache DCR's */
121 cache-line-size = <32>; /* 32 bytes */
122 cache-size = <262144>; /* L2, 256K */
123 interrupt-parent = <&UIC1>;
124 interrupts = <11 1>;

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274 reg = <0xef600400 0x00000008>;
275 virtual-reg = <0xef600400>;
276 clock-frequency = <0>; /* Filled in by U-Boot */
277 current-speed = <0>; /* Filled in by U-Boot */
278 interrupt-parent = <&UIC0>;
279 interrupts = <0x1 0x4>;
280 };
281
273 UART2: serial@ef600500 {
274 device_type = "serial";
275 compatible = "ns16550";
276 reg = <0xef600500 0x00000008>;
277 virtual-reg = <0xef600500>;
278 clock-frequency = <0>; /* Filled in by U-Boot */
279 current-speed = <0>; /* Filled in by U-Boot */
280 interrupt-parent = <&UIC1>;
281 interrupts = <28 0x4>;
282 };
283
284 UART3: serial@ef600600 {
285 device_type = "serial";
286 compatible = "ns16550";
287 reg = <0xef600600 0x00000008>;
288 virtual-reg = <0xef600600>;
289 clock-frequency = <0>; /* Filled in by U-Boot */
290 current-speed = <0>; /* Filled in by U-Boot */
291 interrupt-parent = <&UIC1>;
292 interrupts = <29 0x4>;
293 };
294
295 IIC0: i2c@ef600700 {
296 compatible = "ibm,iic-460ex", "ibm,iic";
297 reg = <0xef600700 0x00000014>;
298 interrupt-parent = <&UIC0>;
299 interrupts = <0x2 0x4>;
300 #address-cells = <1>;
301 #size-cells = <0>;
302 rtc@68 {

--- 221 unchanged lines hidden --- 		282 IIC0: i2c@ef600700 {
283 compatible = "ibm,iic-460ex", "ibm,iic";
284 reg = <0xef600700 0x00000014>;
285 interrupt-parent = <&UIC0>;
286 interrupts = <0x2 0x4>;
287 #address-cells = <1>;
288 #size-cells = <0>;
289 rtc@68 {

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