canyonlands.dts (84d727a109081684c2e01b811cb0d6dc3b9380ca) canyonlands.dts (cd85400a022335a92fa3c25827179a7ad5e02225)
1/*
2 * Device Tree Source for AMCC Canyonlands (460EX)
3 *
4 * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without
8 * any warranty of any kind, whether express or implied.

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35 clock-frequency = <0>; /* Filled in by U-Boot */
36 timebase-frequency = <0>; /* Filled in by U-Boot */
37 i-cache-line-size = <32>;
38 d-cache-line-size = <32>;
39 i-cache-size = <32768>;
40 d-cache-size = <32768>;
41 dcr-controller;
42 dcr-access-method = "native";
1/*
2 * Device Tree Source for AMCC Canyonlands (460EX)
3 *
4 * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without
8 * any warranty of any kind, whether express or implied.

--- 26 unchanged lines hidden (view full) ---

35 clock-frequency = <0>; /* Filled in by U-Boot */
36 timebase-frequency = <0>; /* Filled in by U-Boot */
37 i-cache-line-size = <32>;
38 d-cache-line-size = <32>;
39 i-cache-size = <32768>;
40 d-cache-size = <32768>;
41 dcr-controller;
42 dcr-access-method = "native";
43 next-level-cache = <&L2C0>;
43 };
44 };
45
46 memory {
47 device_type = "memory";
48 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
49 };
50

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99 dcr-reg = <0x00e 0x002>;
100 };
101
102 CPR0: cpr {
103 compatible = "ibm,cpr-460ex";
104 dcr-reg = <0x00c 0x002>;
105 };
106
44 };
45 };
46
47 memory {
48 device_type = "memory";
49 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
50 };
51

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100 dcr-reg = <0x00e 0x002>;
101 };
102
103 CPR0: cpr {
104 compatible = "ibm,cpr-460ex";
105 dcr-reg = <0x00c 0x002>;
106 };
107
108 L2C0: l2c {
109 compatible = "ibm,l2-cache-460ex", "ibm,l2-cache";
110 dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */
111 0x030 0x008>; /* L2 cache DCR's */
112 cache-line-size = <32>; /* 32 bytes */
113 cache-size = <262144>; /* L2, 256K */
114 interrupt-parent = <&UIC1>;
115 interrupts = <11 1>;
116 };
117
107 plb {
108 compatible = "ibm,plb-460ex", "ibm,plb4";
109 #address-cells = <2>;
110 #size-cells = <1>;
111 ranges;
112 clock-frequency = <0>; /* Filled in by U-Boot */
113
114 SDRAM0: sdram {

--- 330 unchanged lines hidden --- 		118 plb {
119 compatible = "ibm,plb-460ex", "ibm,plb4";
120 #address-cells = <2>;
121 #size-cells = <1>;
122 ranges;
123 clock-frequency = <0>; /* Filled in by U-Boot */
124
125 SDRAM0: sdram {

--- 330 unchanged lines hidden ---