canyonlands.dts (7022b15e2a9f878fd5184586064c63352c3dd225) canyonlands.dts (71f349799b34c8b6ce3df42126b4de6cfa16456d)
1/*
2 * Device Tree Source for AMCC Canyonlands (460EX)
3 *
4 * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without
8 * any warranty of any kind, whether express or implied.
9 */
10
1/*
2 * Device Tree Source for AMCC Canyonlands (460EX)
3 *
4 * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without
8 * any warranty of any kind, whether express or implied.
9 */
10
11/dts-v1/;
12
11/ {
12 #address-cells = <2>;
13 #size-cells = <1>;
14 model = "amcc,canyonlands";
15 compatible = "amcc,canyonlands";
13/ {
14 #address-cells = <2>;
15 #size-cells = <1>;
16 model = "amcc,canyonlands";
17 compatible = "amcc,canyonlands";
16 dcr-parent = <&/cpus/cpu@0>;
18 dcr-parent = <&{/cpus/cpu@0}>;
17
18 aliases {
19 ethernet0 = &EMAC0;
20 ethernet1 = &EMAC1;
21 serial0 = &UART0;
22 serial1 = &UART1;
23 };
24
25 cpus {
26 #address-cells = <1>;
27 #size-cells = <0>;
28
29 cpu@0 {
30 device_type = "cpu";
31 model = "PowerPC,460EX";
19
20 aliases {
21 ethernet0 = &EMAC0;
22 ethernet1 = &EMAC1;
23 serial0 = &UART0;
24 serial1 = &UART1;
25 };
26
27 cpus {
28 #address-cells = <1>;
29 #size-cells = <0>;
30
31 cpu@0 {
32 device_type = "cpu";
33 model = "PowerPC,460EX";
32 reg = <0>;
34 reg = <0x00000000>;
33 clock-frequency = <0>; /* Filled in by U-Boot */
34 timebase-frequency = <0>; /* Filled in by U-Boot */
35 clock-frequency = <0>; /* Filled in by U-Boot */
36 timebase-frequency = <0>; /* Filled in by U-Boot */
35 i-cache-line-size = <20>;
36 d-cache-line-size = <20>;
37 i-cache-size = <8000>;
38 d-cache-size = <8000>;
37 i-cache-line-size = <32>;
38 d-cache-line-size = <32>;
39 i-cache-size = <32768>;
40 d-cache-size = <32768>;
39 dcr-controller;
40 dcr-access-method = "native";
41 };
42 };
43
44 memory {
45 device_type = "memory";
41 dcr-controller;
42 dcr-access-method = "native";
43 };
44 };
45
46 memory {
47 device_type = "memory";
46 reg = <0 0 0>; /* Filled in by U-Boot */
48 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
47 };
48
49 UIC0: interrupt-controller0 {
50 compatible = "ibm,uic-460ex","ibm,uic";
51 interrupt-controller;
52 cell-index = <0>;
49 };
50
51 UIC0: interrupt-controller0 {
52 compatible = "ibm,uic-460ex","ibm,uic";
53 interrupt-controller;
54 cell-index = <0>;
53 dcr-reg = <0c0 009>;
55 dcr-reg = <0x0c0 0x009>;
54 #address-cells = <0>;
55 #size-cells = <0>;
56 #interrupt-cells = <2>;
57 };
58
59 UIC1: interrupt-controller1 {
60 compatible = "ibm,uic-460ex","ibm,uic";
61 interrupt-controller;
62 cell-index = <1>;
56 #address-cells = <0>;
57 #size-cells = <0>;
58 #interrupt-cells = <2>;
59 };
60
61 UIC1: interrupt-controller1 {
62 compatible = "ibm,uic-460ex","ibm,uic";
63 interrupt-controller;
64 cell-index = <1>;
63 dcr-reg = <0d0 009>;
65 dcr-reg = <0x0d0 0x009>;
64 #address-cells = <0>;
65 #size-cells = <0>;
66 #interrupt-cells = <2>;
66 #address-cells = <0>;
67 #size-cells = <0>;
68 #interrupt-cells = <2>;
67 interrupts = <1e 4 1f 4>; /* cascade */
69 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
68 interrupt-parent = <&UIC0>;
69 };
70
71 UIC2: interrupt-controller2 {
72 compatible = "ibm,uic-460ex","ibm,uic";
73 interrupt-controller;
74 cell-index = <2>;
70 interrupt-parent = <&UIC0>;
71 };
72
73 UIC2: interrupt-controller2 {
74 compatible = "ibm,uic-460ex","ibm,uic";
75 interrupt-controller;
76 cell-index = <2>;
75 dcr-reg = <0e0 009>;
77 dcr-reg = <0x0e0 0x009>;
76 #address-cells = <0>;
77 #size-cells = <0>;
78 #interrupt-cells = <2>;
78 #address-cells = <0>;
79 #size-cells = <0>;
80 #interrupt-cells = <2>;
79 interrupts = <a 4 b 4>; /* cascade */
81 interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
80 interrupt-parent = <&UIC0>;
81 };
82
83 UIC3: interrupt-controller3 {
84 compatible = "ibm,uic-460ex","ibm,uic";
85 interrupt-controller;
86 cell-index = <3>;
82 interrupt-parent = <&UIC0>;
83 };
84
85 UIC3: interrupt-controller3 {
86 compatible = "ibm,uic-460ex","ibm,uic";
87 interrupt-controller;
88 cell-index = <3>;
87 dcr-reg = <0f0 009>;
89 dcr-reg = <0x0f0 0x009>;
88 #address-cells = <0>;
89 #size-cells = <0>;
90 #interrupt-cells = <2>;
90 #address-cells = <0>;
91 #size-cells = <0>;
92 #interrupt-cells = <2>;
91 interrupts = <10 4 11 4>; /* cascade */
93 interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
92 interrupt-parent = <&UIC0>;
93 };
94
95 SDR0: sdr {
96 compatible = "ibm,sdr-460ex";
94 interrupt-parent = <&UIC0>;
95 };
96
97 SDR0: sdr {
98 compatible = "ibm,sdr-460ex";
97 dcr-reg = <00e 002>;
99 dcr-reg = <0x00e 0x002>;
98 };
99
100 CPR0: cpr {
101 compatible = "ibm,cpr-460ex";
100 };
101
102 CPR0: cpr {
103 compatible = "ibm,cpr-460ex";
102 dcr-reg = <00c 002>;
104 dcr-reg = <0x00c 0x002>;
103 };
104
105 plb {
106 compatible = "ibm,plb-460ex", "ibm,plb4";
107 #address-cells = <2>;
108 #size-cells = <1>;
109 ranges;
110 clock-frequency = <0>; /* Filled in by U-Boot */
111
112 SDRAM0: sdram {
113 compatible = "ibm,sdram-460ex", "ibm,sdram-405gp";
105 };
106
107 plb {
108 compatible = "ibm,plb-460ex", "ibm,plb4";
109 #address-cells = <2>;
110 #size-cells = <1>;
111 ranges;
112 clock-frequency = <0>; /* Filled in by U-Boot */
113
114 SDRAM0: sdram {
115 compatible = "ibm,sdram-460ex", "ibm,sdram-405gp";
114 dcr-reg = <010 2>;
116 dcr-reg = <0x010 0x002>;
115 };
116
117 MAL0: mcmal {
118 compatible = "ibm,mcmal-460ex", "ibm,mcmal2";
117 };
118
119 MAL0: mcmal {
120 compatible = "ibm,mcmal-460ex", "ibm,mcmal2";
119 dcr-reg = <180 62>;
121 dcr-reg = <0x180 0x062>;
120 num-tx-chans = <2>;
122 num-tx-chans = <2>;
121 num-rx-chans = <10>;
123 num-rx-chans = <16>;
122 #address-cells = <0>;
123 #size-cells = <0>;
124 interrupt-parent = <&UIC2>;
124 #address-cells = <0>;
125 #size-cells = <0>;
126 interrupt-parent = <&UIC2>;
125 interrupts = < /*TXEOB*/ 6 4
126 /*RXEOB*/ 7 4
127 /*SERR*/ 3 4
128 /*TXDE*/ 4 4
129 /*RXDE*/ 5 4>;
127 interrupts = < /*TXEOB*/ 0x6 0x4
128 /*RXEOB*/ 0x7 0x4
129 /*SERR*/ 0x3 0x4
130 /*TXDE*/ 0x4 0x4
131 /*RXDE*/ 0x5 0x4>;
130 };
131
132 POB0: opb {
133 compatible = "ibm,opb-460ex", "ibm,opb";
134 #address-cells = <1>;
135 #size-cells = <1>;
132 };
133
134 POB0: opb {
135 compatible = "ibm,opb-460ex", "ibm,opb";
136 #address-cells = <1>;
137 #size-cells = <1>;
136 ranges = <b0000000 4 b0000000 50000000>;
138 ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
137 clock-frequency = <0>; /* Filled in by U-Boot */
138
139 EBC0: ebc {
140 compatible = "ibm,ebc-460ex", "ibm,ebc";
139 clock-frequency = <0>; /* Filled in by U-Boot */
140
141 EBC0: ebc {
142 compatible = "ibm,ebc-460ex", "ibm,ebc";
141 dcr-reg = <012 2>;
143 dcr-reg = <0x012 0x002>;
142 #address-cells = <2>;
143 #size-cells = <1>;
144 clock-frequency = <0>; /* Filled in by U-Boot */
145 /* ranges property is supplied by U-Boot */
144 #address-cells = <2>;
145 #size-cells = <1>;
146 clock-frequency = <0>; /* Filled in by U-Boot */
147 /* ranges property is supplied by U-Boot */
146 interrupts = <6 4>;
148 interrupts = <0x6 0x4>;
147 interrupt-parent = <&UIC1>;
148
149 nor_flash@0,0 {
150 compatible = "amd,s29gl512n", "cfi-flash";
151 bank-width = <2>;
149 interrupt-parent = <&UIC1>;
150
151 nor_flash@0,0 {
152 compatible = "amd,s29gl512n", "cfi-flash";
153 bank-width = <2>;
152 reg = <0 000000 4000000>;
154 reg = <0x00000000 0x00000000 0x04000000>;
153 #address-cells = <1>;
154 #size-cells = <1>;
155 partition@0 {
156 label = "kernel";
155 #address-cells = <1>;
156 #size-cells = <1>;
157 partition@0 {
158 label = "kernel";
157 reg = <0 1e0000>;
159 reg = <0x00000000 0x001e0000>;
158 };
159 partition@1e0000 {
160 label = "dtb";
160 };
161 partition@1e0000 {
162 label = "dtb";
161 reg = <1e0000 20000>;
163 reg = <0x001e0000 0x00020000>;
162 };
163 partition@200000 {
164 label = "ramdisk";
164 };
165 partition@200000 {
166 label = "ramdisk";
165 reg = <200000 1400000>;
167 reg = <0x00200000 0x01400000>;
166 };
167 partition@1600000 {
168 label = "jffs2";
168 };
169 partition@1600000 {
170 label = "jffs2";
169 reg = <1600000 400000>;
171 reg = <0x01600000 0x00400000>;
170 };
171 partition@1a00000 {
172 label = "user";
172 };
173 partition@1a00000 {
174 label = "user";
173 reg = <1a00000 2560000>;
175 reg = <0x01a00000 0x02560000>;
174 };
175 partition@3f60000 {
176 label = "env";
176 };
177 partition@3f60000 {
178 label = "env";
177 reg = <3f60000 40000>;
179 reg = <0x03f60000 0x00040000>;
178 };
179 partition@3fa0000 {
180 label = "u-boot";
180 };
181 partition@3fa0000 {
182 label = "u-boot";
181 reg = <3fa0000 60000>;
183 reg = <0x03fa0000 0x00060000>;
182 };
183 };
184 };
185
186 UART0: serial@ef600300 {
187 device_type = "serial";
188 compatible = "ns16550";
184 };
185 };
186 };
187
188 UART0: serial@ef600300 {
189 device_type = "serial";
190 compatible = "ns16550";
189 reg = <ef600300 8>;
190 virtual-reg = <ef600300>;
191 reg = <0xef600300 0x00000008>;
192 virtual-reg = <0xef600300>;
191 clock-frequency = <0>; /* Filled in by U-Boot */
192 current-speed = <0>; /* Filled in by U-Boot */
193 interrupt-parent = <&UIC1>;
193 clock-frequency = <0>; /* Filled in by U-Boot */
194 current-speed = <0>; /* Filled in by U-Boot */
195 interrupt-parent = <&UIC1>;
194 interrupts = <1 4>;
196 interrupts = <0x1 0x4>;
195 };
196
197 UART1: serial@ef600400 {
198 device_type = "serial";
199 compatible = "ns16550";
197 };
198
199 UART1: serial@ef600400 {
200 device_type = "serial";
201 compatible = "ns16550";
200 reg = <ef600400 8>;
201 virtual-reg = <ef600400>;
202 reg = <0xef600400 0x00000008>;
203 virtual-reg = <0xef600400>;
202 clock-frequency = <0>; /* Filled in by U-Boot */
203 current-speed = <0>; /* Filled in by U-Boot */
204 interrupt-parent = <&UIC0>;
204 clock-frequency = <0>; /* Filled in by U-Boot */
205 current-speed = <0>; /* Filled in by U-Boot */
206 interrupt-parent = <&UIC0>;
205 interrupts = <1 4>;
207 interrupts = <0x1 0x4>;
206 };
207
208 UART2: serial@ef600500 {
209 device_type = "serial";
210 compatible = "ns16550";
208 };
209
210 UART2: serial@ef600500 {
211 device_type = "serial";
212 compatible = "ns16550";
211 reg = <ef600500 8>;
212 virtual-reg = <ef600500>;
213 reg = <0xef600500 0x00000008>;
214 virtual-reg = <0xef600500>;
213 clock-frequency = <0>; /* Filled in by U-Boot */
214 current-speed = <0>; /* Filled in by U-Boot */
215 interrupt-parent = <&UIC1>;
215 clock-frequency = <0>; /* Filled in by U-Boot */
216 current-speed = <0>; /* Filled in by U-Boot */
217 interrupt-parent = <&UIC1>;
216 interrupts = <1d 4>;
218 interrupts = <0x1d 0x4>;
217 };
218
219 UART3: serial@ef600600 {
220 device_type = "serial";
221 compatible = "ns16550";
219 };
220
221 UART3: serial@ef600600 {
222 device_type = "serial";
223 compatible = "ns16550";
222 reg = <ef600600 8>;
223 virtual-reg = <ef600600>;
224 reg = <0xef600600 0x00000008>;
225 virtual-reg = <0xef600600>;
224 clock-frequency = <0>; /* Filled in by U-Boot */
225 current-speed = <0>; /* Filled in by U-Boot */
226 interrupt-parent = <&UIC1>;
226 clock-frequency = <0>; /* Filled in by U-Boot */
227 current-speed = <0>; /* Filled in by U-Boot */
228 interrupt-parent = <&UIC1>;
227 interrupts = <1e 4>;
229 interrupts = <0x1e 0x4>;
228 };
229
230 IIC0: i2c@ef600700 {
231 compatible = "ibm,iic-460ex", "ibm,iic";
230 };
231
232 IIC0: i2c@ef600700 {
233 compatible = "ibm,iic-460ex", "ibm,iic";
232 reg = <ef600700 14>;
234 reg = <0xef600700 0x00000014>;
233 interrupt-parent = <&UIC0>;
235 interrupt-parent = <&UIC0>;
234 interrupts = <2 4>;
236 interrupts = <0x2 0x4>;
235 };
236
237 IIC1: i2c@ef600800 {
238 compatible = "ibm,iic-460ex", "ibm,iic";
237 };
238
239 IIC1: i2c@ef600800 {
240 compatible = "ibm,iic-460ex", "ibm,iic";
239 reg = <ef600800 14>;
241 reg = <0xef600800 0x00000014>;
240 interrupt-parent = <&UIC0>;
242 interrupt-parent = <&UIC0>;
241 interrupts = <3 4>;
243 interrupts = <0x3 0x4>;
242 };
243
244 ZMII0: emac-zmii@ef600d00 {
245 compatible = "ibm,zmii-460ex", "ibm,zmii";
244 };
245
246 ZMII0: emac-zmii@ef600d00 {
247 compatible = "ibm,zmii-460ex", "ibm,zmii";
246 reg = <ef600d00 c>;
248 reg = <0xef600d00 0x0000000c>;
247 };
248
249 RGMII0: emac-rgmii@ef601500 {
250 compatible = "ibm,rgmii-460ex", "ibm,rgmii";
249 };
250
251 RGMII0: emac-rgmii@ef601500 {
252 compatible = "ibm,rgmii-460ex", "ibm,rgmii";
251 reg = <ef601500 8>;
253 reg = <0xef601500 0x00000008>;
252 has-mdio;
253 };
254
255 TAH0: emac-tah@ef601350 {
256 compatible = "ibm,tah-460ex", "ibm,tah";
254 has-mdio;
255 };
256
257 TAH0: emac-tah@ef601350 {
258 compatible = "ibm,tah-460ex", "ibm,tah";
257 reg = <ef601350 30>;
259 reg = <0xef601350 0x00000030>;
258 };
259
260 TAH1: emac-tah@ef601450 {
261 compatible = "ibm,tah-460ex", "ibm,tah";
260 };
261
262 TAH1: emac-tah@ef601450 {
263 compatible = "ibm,tah-460ex", "ibm,tah";
262 reg = <ef601450 30>;
264 reg = <0xef601450 0x00000030>;
263 };
264
265 EMAC0: ethernet@ef600e00 {
266 device_type = "network";
267 compatible = "ibm,emac-460ex", "ibm,emac4";
268 interrupt-parent = <&EMAC0>;
265 };
266
267 EMAC0: ethernet@ef600e00 {
268 device_type = "network";
269 compatible = "ibm,emac-460ex", "ibm,emac4";
270 interrupt-parent = <&EMAC0>;
269 interrupts = <0 1>;
271 interrupts = <0x0 0x1>;
270 #interrupt-cells = <1>;
271 #address-cells = <0>;
272 #size-cells = <0>;
272 #interrupt-cells = <1>;
273 #address-cells = <0>;
274 #size-cells = <0>;
273 interrupt-map = </*Status*/ 0 &UIC2 10 4
274 /*Wake*/ 1 &UIC2 14 4>;
275 reg = <ef600e00 70>;
275 interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4
276 /*Wake*/ 0x1 &UIC2 0x14 0x4>;
277 reg = <0xef600e00 0x00000070>;
276 local-mac-address = [000000000000]; /* Filled in by U-Boot */
277 mal-device = <&MAL0>;
278 mal-tx-channel = <0>;
279 mal-rx-channel = <0>;
280 cell-index = <0>;
278 local-mac-address = [000000000000]; /* Filled in by U-Boot */
279 mal-device = <&MAL0>;
280 mal-tx-channel = <0>;
281 mal-rx-channel = <0>;
282 cell-index = <0>;
281 max-frame-size = <2328>;
282 rx-fifo-size = <1000>;
283 tx-fifo-size = <800>;
283 max-frame-size = <9000>;
284 rx-fifo-size = <4096>;
285 tx-fifo-size = <2048>;
284 phy-mode = "rgmii";
286 phy-mode = "rgmii";
285 phy-map = <00000000>;
287 phy-map = <0x00000000>;
286 rgmii-device = <&RGMII0>;
287 rgmii-channel = <0>;
288 tah-device = <&TAH0>;
289 tah-channel = <0>;
290 has-inverted-stacr-oc;
291 has-new-stacr-staopc;
292 };
293
294 EMAC1: ethernet@ef600f00 {
295 device_type = "network";
296 compatible = "ibm,emac-460ex", "ibm,emac4";
297 interrupt-parent = <&EMAC1>;
288 rgmii-device = <&RGMII0>;
289 rgmii-channel = <0>;
290 tah-device = <&TAH0>;
291 tah-channel = <0>;
292 has-inverted-stacr-oc;
293 has-new-stacr-staopc;
294 };
295
296 EMAC1: ethernet@ef600f00 {
297 device_type = "network";
298 compatible = "ibm,emac-460ex", "ibm,emac4";
299 interrupt-parent = <&EMAC1>;
298 interrupts = <0 1>;
300 interrupts = <0x0 0x1>;
299 #interrupt-cells = <1>;
300 #address-cells = <0>;
301 #size-cells = <0>;
301 #interrupt-cells = <1>;
302 #address-cells = <0>;
303 #size-cells = <0>;
302 interrupt-map = </*Status*/ 0 &UIC2 11 4
303 /*Wake*/ 1 &UIC2 15 4>;
304 reg = <ef600f00 70>;
304 interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4
305 /*Wake*/ 0x1 &UIC2 0x15 0x4>;
306 reg = <0xef600f00 0x00000070>;
305 local-mac-address = [000000000000]; /* Filled in by U-Boot */
306 mal-device = <&MAL0>;
307 mal-tx-channel = <1>;
308 mal-rx-channel = <8>;
309 cell-index = <1>;
307 local-mac-address = [000000000000]; /* Filled in by U-Boot */
308 mal-device = <&MAL0>;
309 mal-tx-channel = <1>;
310 mal-rx-channel = <8>;
311 cell-index = <1>;
310 max-frame-size = <2328>;
311 rx-fifo-size = <1000>;
312 tx-fifo-size = <800>;
312 max-frame-size = <9000>;
313 rx-fifo-size = <4096>;
314 tx-fifo-size = <2048>;
313 phy-mode = "rgmii";
315 phy-mode = "rgmii";
314 phy-map = <00000000>;
316 phy-map = <0x00000000>;
315 rgmii-device = <&RGMII0>;
316 rgmii-channel = <1>;
317 tah-device = <&TAH1>;
318 tah-channel = <1>;
319 has-inverted-stacr-oc;
320 has-new-stacr-staopc;
321 mdio-device = <&EMAC0>;
322 };
323 };
324
325 PCIX0: pci@c0ec00000 {
326 device_type = "pci";
327 #interrupt-cells = <1>;
328 #size-cells = <2>;
329 #address-cells = <3>;
330 compatible = "ibm,plb-pcix-460ex", "ibm,plb-pcix";
331 primary;
332 large-inbound-windows;
333 enable-msi-hole;
317 rgmii-device = <&RGMII0>;
318 rgmii-channel = <1>;
319 tah-device = <&TAH1>;
320 tah-channel = <1>;
321 has-inverted-stacr-oc;
322 has-new-stacr-staopc;
323 mdio-device = <&EMAC0>;
324 };
325 };
326
327 PCIX0: pci@c0ec00000 {
328 device_type = "pci";
329 #interrupt-cells = <1>;
330 #size-cells = <2>;
331 #address-cells = <3>;
332 compatible = "ibm,plb-pcix-460ex", "ibm,plb-pcix";
333 primary;
334 large-inbound-windows;
335 enable-msi-hole;
334 reg = <c 0ec00000 8 /* Config space access */
335 0 0 0 /* no IACK cycles */
336 c 0ed00000 4 /* Special cycles */
337 c 0ec80000 100 /* Internal registers */
338 c 0ec80100 fc>; /* Internal messaging registers */
336 reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */
337 0x00000000 0x00000000 0x00000000 /* no IACK cycles */
338 0x0000000c 0x0ed00000 0x00000004 /* Special cycles */
339 0x0000000c 0x0ec80000 0x00000100 /* Internal registers */
340 0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */
339
340 /* Outbound ranges, one memory and one IO,
341 * later cannot be changed
342 */
341
342 /* Outbound ranges, one memory and one IO,
343 * later cannot be changed
344 */
343 ranges = <02000000 0 80000000 0000000d 80000000 0 80000000
344 01000000 0 00000000 0000000c 08000000 0 00010000>;
345 ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000
346 0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>;
345
346 /* Inbound 2GB range starting at 0 */
347
348 /* Inbound 2GB range starting at 0 */
347 dma-ranges = <42000000 0 0 0 0 0 80000000>;
349 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
348
349 /* This drives busses 0 to 0x3f */
350
351 /* This drives busses 0 to 0x3f */
350 bus-range = <0 3f>;
352 bus-range = <0x0 0x3f>;
351
352 /* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */
353
354 /* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */
353 interrupt-map-mask = <0000 0 0 0>;
354 interrupt-map = < 0000 0 0 0 &UIC1 0 8 >;
355 interrupt-map-mask = <0x0 0x0 0x0 0x0>;
356 interrupt-map = < 0x0 0x0 0x0 0x0 &UIC1 0x0 0x8 >;
355 };
356
357 PCIE0: pciex@d00000000 {
358 device_type = "pci";
359 #interrupt-cells = <1>;
360 #size-cells = <2>;
361 #address-cells = <3>;
362 compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
363 primary;
357 };
358
359 PCIE0: pciex@d00000000 {
360 device_type = "pci";
361 #interrupt-cells = <1>;
362 #size-cells = <2>;
363 #address-cells = <3>;
364 compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
365 primary;
364 port = <0>; /* port number */
365 reg = <d 00000000 20000000 /* Config space access */
366 c 08010000 00001000>; /* Registers */
367 dcr-reg = <100 020>;
368 sdr-base = <300>;
366 port = <0x0>; /* port number */
367 reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */
368 0x0000000c 0x08010000 0x00001000>; /* Registers */
369 dcr-reg = <0x100 0x020>;
370 sdr-base = <0x300>;
369
370 /* Outbound ranges, one memory and one IO,
371 * later cannot be changed
372 */
371
372 /* Outbound ranges, one memory and one IO,
373 * later cannot be changed
374 */
373 ranges = <02000000 0 80000000 0000000e 00000000 0 80000000
374 01000000 0 00000000 0000000f 80000000 0 00010000>;
375 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
376 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
375
376 /* Inbound 2GB range starting at 0 */
377
378 /* Inbound 2GB range starting at 0 */
377 dma-ranges = <42000000 0 0 0 0 0 80000000>;
379 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
378
379 /* This drives busses 40 to 0x7f */
380
381 /* This drives busses 40 to 0x7f */
380 bus-range = <40 7f>;
382 bus-range = <0x40 0x7f>;
381
382 /* Legacy interrupts (note the weird polarity, the bridge seems
383 * to invert PCIe legacy interrupts).
384 * We are de-swizzling here because the numbers are actually for
385 * port of the root complex virtual P2P bridge. But I want
386 * to avoid putting a node for it in the tree, so the numbers
387 * below are basically de-swizzled numbers.
388 * The real slot is on idsel 0, so the swizzling is 1:1
389 */
383
384 /* Legacy interrupts (note the weird polarity, the bridge seems
385 * to invert PCIe legacy interrupts).
386 * We are de-swizzling here because the numbers are actually for
387 * port of the root complex virtual P2P bridge. But I want
388 * to avoid putting a node for it in the tree, so the numbers
389 * below are basically de-swizzled numbers.
390 * The real slot is on idsel 0, so the swizzling is 1:1
391 */
390 interrupt-map-mask = <0000 0 0 7>;
392 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
391 interrupt-map = <
393 interrupt-map = <
392 0000 0 0 1 &UIC3 c 4 /* swizzled int A */
393 0000 0 0 2 &UIC3 d 4 /* swizzled int B */
394 0000 0 0 3 &UIC3 e 4 /* swizzled int C */
395 0000 0 0 4 &UIC3 f 4 /* swizzled int D */>;
394 0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */
395 0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */
396 0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */
397 0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>;
396 };
397
398 PCIE1: pciex@d20000000 {
399 device_type = "pci";
400 #interrupt-cells = <1>;
401 #size-cells = <2>;
402 #address-cells = <3>;
403 compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
404 primary;
398 };
399
400 PCIE1: pciex@d20000000 {
401 device_type = "pci";
402 #interrupt-cells = <1>;
403 #size-cells = <2>;
404 #address-cells = <3>;
405 compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
406 primary;
405 port = <1>; /* port number */
406 reg = <d 20000000 20000000 /* Config space access */
407 c 08011000 00001000>; /* Registers */
408 dcr-reg = <120 020>;
409 sdr-base = <340>;
407 port = <0x1>; /* port number */
408 reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */
409 0x0000000c 0x08011000 0x00001000>; /* Registers */
410 dcr-reg = <0x120 0x020>;
411 sdr-base = <0x340>;
410
411 /* Outbound ranges, one memory and one IO,
412 * later cannot be changed
413 */
412
413 /* Outbound ranges, one memory and one IO,
414 * later cannot be changed
415 */
414 ranges = <02000000 0 80000000 0000000e 80000000 0 80000000
415 01000000 0 00000000 0000000f 80010000 0 00010000>;
416 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000
417 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>;
416
417 /* Inbound 2GB range starting at 0 */
418
419 /* Inbound 2GB range starting at 0 */
418 dma-ranges = <42000000 0 0 0 0 0 80000000>;
420 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
419
420 /* This drives busses 80 to 0xbf */
421
422 /* This drives busses 80 to 0xbf */
421 bus-range = <80 bf>;
423 bus-range = <0x80 0xbf>;
422
423 /* Legacy interrupts (note the weird polarity, the bridge seems
424 * to invert PCIe legacy interrupts).
425 * We are de-swizzling here because the numbers are actually for
426 * port of the root complex virtual P2P bridge. But I want
427 * to avoid putting a node for it in the tree, so the numbers
428 * below are basically de-swizzled numbers.
429 * The real slot is on idsel 0, so the swizzling is 1:1
430 */
424
425 /* Legacy interrupts (note the weird polarity, the bridge seems
426 * to invert PCIe legacy interrupts).
427 * We are de-swizzling here because the numbers are actually for
428 * port of the root complex virtual P2P bridge. But I want
429 * to avoid putting a node for it in the tree, so the numbers
430 * below are basically de-swizzled numbers.
431 * The real slot is on idsel 0, so the swizzling is 1:1
432 */
431 interrupt-map-mask = <0000 0 0 7>;
433 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
432 interrupt-map = <
434 interrupt-map = <
433 0000 0 0 1 &UIC3 10 4 /* swizzled int A */
434 0000 0 0 2 &UIC3 11 4 /* swizzled int B */
435 0000 0 0 3 &UIC3 12 4 /* swizzled int C */
436 0000 0 0 4 &UIC3 13 4 /* swizzled int D */>;
435 0x0 0x0 0x0 0x1 &UIC3 0x10 0x4 /* swizzled int A */
436 0x0 0x0 0x0 0x2 &UIC3 0x11 0x4 /* swizzled int B */
437 0x0 0x0 0x0 0x3 &UIC3 0x12 0x4 /* swizzled int C */
438 0x0 0x0 0x0 0x4 &UIC3 0x13 0x4 /* swizzled int D */>;
437 };
438 };
439};
439 };
440 };
441};