akebono.dts (597473720f4dc69749542bfcfed4a927a43d935e) akebono.dts (86bc917d2ac117ec922dbf8ed92ca989bf333281)
1/*
2 * Device Tree Source for IBM Embedded PPC 476 Platform
3 *
4 * Copyright © 2013 Tony Breeds IBM Corporation
5 * Copyright © 2013 Alistair Popple IBM Corporation
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without

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243 };
244
245 FPGA0: fpga@ebc00000 {
246 compatible = "ibm,akebono-fpga";
247 reg = <0xebc00000 0x8>;
248 };
249 };
250
1/*
2 * Device Tree Source for IBM Embedded PPC 476 Platform
3 *
4 * Copyright © 2013 Tony Breeds IBM Corporation
5 * Copyright © 2013 Alistair Popple IBM Corporation
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without

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243 };
244
245 FPGA0: fpga@ebc00000 {
246 compatible = "ibm,akebono-fpga";
247 reg = <0xebc00000 0x8>;
248 };
249 };
250
251 PCIE0: pciex@10100000000 {
251 PCIE0: pcie@10100000000 {
252 device_type = "pci";
253 #interrupt-cells = <1>;
254 #size-cells = <2>;
255 #address-cells = <3>;
256 compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
257 primary;
258 port = <0x0>; /* port number */
259 reg = <0x00000101 0x00000000 0x0 0x10000000 /* Config space access */

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283 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
284 interrupt-map = <
285 0x0 0x0 0x0 0x1 &MPIC 45 0x2 /* int A */
286 0x0 0x0 0x0 0x2 &MPIC 46 0x2 /* int B */
287 0x0 0x0 0x0 0x3 &MPIC 47 0x2 /* int C */
288 0x0 0x0 0x0 0x4 &MPIC 48 0x2 /* int D */>;
289 };
290
252 device_type = "pci";
253 #interrupt-cells = <1>;
254 #size-cells = <2>;
255 #address-cells = <3>;
256 compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
257 primary;
258 port = <0x0>; /* port number */
259 reg = <0x00000101 0x00000000 0x0 0x10000000 /* Config space access */

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283 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
284 interrupt-map = <
285 0x0 0x0 0x0 0x1 &MPIC 45 0x2 /* int A */
286 0x0 0x0 0x0 0x2 &MPIC 46 0x2 /* int B */
287 0x0 0x0 0x0 0x3 &MPIC 47 0x2 /* int C */
288 0x0 0x0 0x0 0x4 &MPIC 48 0x2 /* int D */>;
289 };
290
291 PCIE1: pciex@20100000000 {
291 PCIE1: pcie@20100000000 {
292 device_type = "pci";
293 #interrupt-cells = <1>;
294 #size-cells = <2>;
295 #address-cells = <3>;
296 compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
297 primary;
298 port = <0x1>; /* port number */
299 reg = <0x00000201 0x00000000 0x0 0x10000000 /* Config space access */

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323 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
324 interrupt-map = <
325 0x0 0x0 0x0 0x1 &MPIC 53 0x2 /* int A */
326 0x0 0x0 0x0 0x2 &MPIC 54 0x2 /* int B */
327 0x0 0x0 0x0 0x3 &MPIC 55 0x2 /* int C */
328 0x0 0x0 0x0 0x4 &MPIC 56 0x2 /* int D */>;
329 };
330
292 device_type = "pci";
293 #interrupt-cells = <1>;
294 #size-cells = <2>;
295 #address-cells = <3>;
296 compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
297 primary;
298 port = <0x1>; /* port number */
299 reg = <0x00000201 0x00000000 0x0 0x10000000 /* Config space access */

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323 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
324 interrupt-map = <
325 0x0 0x0 0x0 0x1 &MPIC 53 0x2 /* int A */
326 0x0 0x0 0x0 0x2 &MPIC 54 0x2 /* int B */
327 0x0 0x0 0x0 0x3 &MPIC 55 0x2 /* int C */
328 0x0 0x0 0x0 0x4 &MPIC 56 0x2 /* int D */>;
329 };
330
331 PCIE2: pciex@18100000000 {
331 PCIE2: pcie@18100000000 {
332 device_type = "pci";
333 #interrupt-cells = <1>;
334 #size-cells = <2>;
335 #address-cells = <3>;
336 compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
337 primary;
338 port = <0x2>; /* port number */
339 reg = <0x00000181 0x00000000 0x0 0x10000000 /* Config space access */

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363 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
364 interrupt-map = <
365 0x0 0x0 0x0 0x1 &MPIC 61 0x2 /* int A */
366 0x0 0x0 0x0 0x2 &MPIC 62 0x2 /* int B */
367 0x0 0x0 0x0 0x3 &MPIC 63 0x2 /* int C */
368 0x0 0x0 0x0 0x4 &MPIC 64 0x2 /* int D */>;
369 };
370
332 device_type = "pci";
333 #interrupt-cells = <1>;
334 #size-cells = <2>;
335 #address-cells = <3>;
336 compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
337 primary;
338 port = <0x2>; /* port number */
339 reg = <0x00000181 0x00000000 0x0 0x10000000 /* Config space access */

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363 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
364 interrupt-map = <
365 0x0 0x0 0x0 0x1 &MPIC 61 0x2 /* int A */
366 0x0 0x0 0x0 0x2 &MPIC 62 0x2 /* int B */
367 0x0 0x0 0x0 0x3 &MPIC 63 0x2 /* int C */
368 0x0 0x0 0x0 0x4 &MPIC 64 0x2 /* int D */>;
369 };
370
371 PCIE3: pciex@28100000000 {
371 PCIE3: pcie@28100000000 {
372 device_type = "pci";
373 #interrupt-cells = <1>;
374 #size-cells = <2>;
375 #address-cells = <3>;
376 compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
377 primary;
378 port = <0x3>; /* port number */
379 reg = <0x00000281 0x00000000 0x0 0x10000000 /* Config space access */

--- 36 unchanged lines hidden --- 		372 device_type = "pci";
373 #interrupt-cells = <1>;
374 #size-cells = <2>;
375 #address-cells = <3>;
376 compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
377 primary;
378 port = <0x3>; /* port number */
379 reg = <0x00000281 0x00000000 0x0 0x10000000 /* Config space access */

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