entry.S (f1f76afd71e0f17af9a35fcb649f4bab53304a4d) entry.S (2fd83038160531245099c3c5b3511fa4b80765eb)
1/*
2 * Linux/PA-RISC Project (http://www.parisc-linux.org/)
3 *
4 * kernel entry points (interruptions, system call wrappers)
5 * Copyright (C) 1999,2000 Philipp Rumpf
6 * Copyright (C) 1999 SuSE GmbH Nuernberg
7 * Copyright (C) 2000 Hewlett-Packard (John Marvin)
8 * Copyright (C) 1999 Hewlett-Packard (Frank Rowand)

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497 * first pmd adjacent to the pgd. This means that we can
498 * subtract a constant offset to get to it. The pmd and pgd
499 * sizes are arranged so that a single pmd covers 4GB (giving
500 * a full LP64 process access to 8TB) so our lookups are
501 * effectively L2 for the first 4GB of the kernel (i.e. for
502 * all ILP32 processes and all the kernel for machines with
503 * under 4GB of memory) */
504 .macro L3_ptep pgd,pte,index,va,fault
1/*
2 * Linux/PA-RISC Project (http://www.parisc-linux.org/)
3 *
4 * kernel entry points (interruptions, system call wrappers)
5 * Copyright (C) 1999,2000 Philipp Rumpf
6 * Copyright (C) 1999 SuSE GmbH Nuernberg
7 * Copyright (C) 2000 Hewlett-Packard (John Marvin)
8 * Copyright (C) 1999 Hewlett-Packard (Frank Rowand)

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497 * first pmd adjacent to the pgd. This means that we can
498 * subtract a constant offset to get to it. The pmd and pgd
499 * sizes are arranged so that a single pmd covers 4GB (giving
500 * a full LP64 process access to 8TB) so our lookups are
501 * effectively L2 for the first 4GB of the kernel (i.e. for
502 * all ILP32 processes and all the kernel for machines with
503 * under 4GB of memory) */
504 .macro L3_ptep pgd,pte,index,va,fault
505#if PT_NLEVELS == 3 /* we might have a 2-Level scheme, e.g. with 16kb page size */
505 extrd,u \va,63-ASM_PGDIR_SHIFT,ASM_BITS_PER_PGD,\index
506 copy %r0,\pte
506 extrd,u \va,63-ASM_PGDIR_SHIFT,ASM_BITS_PER_PGD,\index
507 copy %r0,\pte
507 extrd,u,*= \va,31,32,%r0
508 extrd,u,*= \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
508 ldw,s \index(\pgd),\pgd
509 ldw,s \index(\pgd),\pgd
509 extrd,u,*= \va,31,32,%r0
510 extrd,u,*= \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
510 bb,>=,n \pgd,_PxD_PRESENT_BIT,\fault
511 bb,>=,n \pgd,_PxD_PRESENT_BIT,\fault
511 extrd,u,*= \va,31,32,%r0
512 extrd,u,*= \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
512 shld \pgd,PxD_VALUE_SHIFT,\index
513 shld \pgd,PxD_VALUE_SHIFT,\index
513 extrd,u,*= \va,31,32,%r0
514 extrd,u,*= \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
514 copy \index,\pgd
515 copy \index,\pgd
515 extrd,u,*<> \va,31,32,%r0
516 extrd,u,*<> \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
516 ldo ASM_PGD_PMD_OFFSET(\pgd),\pgd
517 ldo ASM_PGD_PMD_OFFSET(\pgd),\pgd
518#endif
517 L2_ptep \pgd,\pte,\index,\va,\fault
518 .endm
519
520 /* Set the _PAGE_ACCESSED bit of the PTE. Be clever and
521 * don't needlessly dirty the cache line if it was already set */
522 .macro update_ptep ptep,pte,tmp,tmp1
523 ldi _PAGE_ACCESSED,\tmp1
524 or \tmp1,\pte,\tmp

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558 extrd,u,*= \pte,_PAGE_USER_BIT+32,1,%r0
559 depdi 7,11,3,\prot
560 /* If we're a gateway page, drop PL2 back to zero for promotion
561 * to kernel privilege (so we can execute the page as kernel).
562 * Any privilege promotion page always denys read and write */
563 extrd,u,*= \pte,_PAGE_GATEWAY_BIT+32,1,%r0
564 depd %r0,11,2,\prot /* If Gateway, Set PL2 to 0 */
565
519 L2_ptep \pgd,\pte,\index,\va,\fault
520 .endm
521
522 /* Set the _PAGE_ACCESSED bit of the PTE. Be clever and
523 * don't needlessly dirty the cache line if it was already set */
524 .macro update_ptep ptep,pte,tmp,tmp1
525 ldi _PAGE_ACCESSED,\tmp1
526 or \tmp1,\pte,\tmp

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560 extrd,u,*= \pte,_PAGE_USER_BIT+32,1,%r0
561 depdi 7,11,3,\prot
562 /* If we're a gateway page, drop PL2 back to zero for promotion
563 * to kernel privilege (so we can execute the page as kernel).
564 * Any privilege promotion page always denys read and write */
565 extrd,u,*= \pte,_PAGE_GATEWAY_BIT+32,1,%r0
566 depd %r0,11,2,\prot /* If Gateway, Set PL2 to 0 */
567
566 /* Get rid of prot bits and convert to page addr for iitlbt and idtlbt */
568 /* Enforce uncacheable pages.
569 * This should ONLY be use for MMIO on PA 2.0 machines.
570 * Memory/DMA is cache coherent on all PA2.0 machines we support
571 * (that means T-class is NOT supported) and the memory controllers
572 * on most of those machines only handles cache transactions.
573 */
574 extrd,u,*= \pte,_PAGE_NO_CACHE_BIT+32,1,%r0
575 depi 1,12,1,\prot
567
576
568 depd %r0,63,PAGE_SHIFT,\pte
569 extrd,s \pte,(63-PAGE_SHIFT)+(63-58),64-PAGE_SHIFT,\pte
577 /* Drop prot bits and convert to page addr for iitlbt and idtlbt */
578 extrd,u \pte,(63-ASM_PFN_PTE_SHIFT)+(63-58),64-PAGE_SHIFT,\pte
579 depdi _PAGE_SIZE_ENCODING_DEFAULT,63,63-58,\pte
570 .endm
571
572 /* Identical macro to make_insert_tlb above, except it
573 * makes the tlb entry for the differently formatted pa11
574 * insertion instructions */
575 .macro make_insert_tlb_11 spc,pte,prot
576 zdep \spc,30,15,\prot
577 dep \pte,8,7,\prot
578 extru,= \pte,_PAGE_NO_CACHE_BIT,1,%r0
579 depi 1,12,1,\prot
580 extru,= \pte,_PAGE_USER_BIT,1,%r0
581 depi 7,11,3,\prot /* Set for user space (1 rsvd for read) */
582 extru,= \pte,_PAGE_GATEWAY_BIT,1,%r0
583 depi 0,11,2,\prot /* If Gateway, Set PL2 to 0 */
584
585 /* Get rid of prot bits and convert to page addr for iitlba */
586
580 .endm
581
582 /* Identical macro to make_insert_tlb above, except it
583 * makes the tlb entry for the differently formatted pa11
584 * insertion instructions */
585 .macro make_insert_tlb_11 spc,pte,prot
586 zdep \spc,30,15,\prot
587 dep \pte,8,7,\prot
588 extru,= \pte,_PAGE_NO_CACHE_BIT,1,%r0
589 depi 1,12,1,\prot
590 extru,= \pte,_PAGE_USER_BIT,1,%r0
591 depi 7,11,3,\prot /* Set for user space (1 rsvd for read) */
592 extru,= \pte,_PAGE_GATEWAY_BIT,1,%r0
593 depi 0,11,2,\prot /* If Gateway, Set PL2 to 0 */
594
595 /* Get rid of prot bits and convert to page addr for iitlba */
596
587 depi 0,31,PAGE_SHIFT,\pte
597 depi _PAGE_SIZE_ENCODING_DEFAULT,31,ASM_PFN_PTE_SHIFT,\pte
588 extru \pte,24,25,\pte
598 extru \pte,24,25,\pte
589
590 .endm
591
592 /* This is for ILP32 PA2.0 only. The TLB insertion needs
593 * to extend into I/O space if the address is 0xfXXXXXXX
594 * so we extend the f's into the top word of the pte in
595 * this case */
596 .macro f_extend pte,tmp
597 extrd,s \pte,42,4,\tmp

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1196
1197 /*
1198 * FIXME: This code has hardwired assumptions about the split
1199 * between space bits and offset bits. This will change
1200 * when we allow alternate page sizes.
1201 */
1202
1203 /* adjust isr/ior. */
599 .endm
600
601 /* This is for ILP32 PA2.0 only. The TLB insertion needs
602 * to extend into I/O space if the address is 0xfXXXXXXX
603 * so we extend the f's into the top word of the pte in
604 * this case */
605 .macro f_extend pte,tmp
606 extrd,s \pte,42,4,\tmp

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1205
1206 /*
1207 * FIXME: This code has hardwired assumptions about the split
1208 * between space bits and offset bits. This will change
1209 * when we allow alternate page sizes.
1210 */
1211
1212 /* adjust isr/ior. */
1204
1205 extrd,u %r16,63,7,%r1 /* get high bits from isr for ior */
1206 depd %r1,31,7,%r17 /* deposit them into ior */
1207 depdi 0,63,7,%r16 /* clear them from isr */
1213 extrd,u %r16,63,SPACEID_SHIFT,%r1 /* get high bits from isr for ior */
1214 depd %r1,31,SPACEID_SHIFT,%r17 /* deposit them into ior */
1215 depdi 0,63,SPACEID_SHIFT,%r16 /* clear them from isr */
1208#endif
1209 STREG %r16, PT_ISR(%r29)
1210 STREG %r17, PT_IOR(%r29)
1211
1212
1213skip_save_ior:
1214 virt_map
1215 save_general %r29

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1216#endif
1217 STREG %r16, PT_ISR(%r29)
1218 STREG %r17, PT_IOR(%r29)
1219
1220
1221skip_save_ior:
1222 virt_map
1223 save_general %r29

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