irq.c (3d5271f9883cba7b54762bc4fe027d4172f06db7) irq.c (e4ac58afdfac792c0583af30dbd9eae53e24c78b)
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1992 Linus Torvalds
7 * Copyright (C) 1994 - 2000 Ralf Baechle
8 */

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14#include <linux/spinlock.h>
15
16#include <asm/i8259.h>
17#include <asm/io.h>
18#include <asm/sni.h>
19
20DEFINE_SPINLOCK(pciasic_lock);
21
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1992 Linus Torvalds
7 * Copyright (C) 1994 - 2000 Ralf Baechle
8 */

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14#include <linux/spinlock.h>
15
16#include <asm/i8259.h>
17#include <asm/io.h>
18#include <asm/sni.h>
19
20DEFINE_SPINLOCK(pciasic_lock);
21
22extern asmlinkage void sni_rm200_pci_handle_int(void);
23
24static void enable_pciasic_irq(unsigned int irq)
25{
26 unsigned int mask = 1 << (irq - PCIMT_IRQ_INT2);
27 unsigned long flags;
28
29 spin_lock_irqsave(&pciasic_lock, flags);
30 *(volatile u8 *) PCIMT_IRQSEL |= mask;
31 spin_unlock_irqrestore(&pciasic_lock, flags);

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66 .ack = mask_and_ack_pciasic_irq,
67 .end = end_pciasic_irq,
68};
69
70/*
71 * hwint0 should deal with MP agent, ASIC PCI, EISA NMI and debug
72 * button interrupts. Later ...
73 */
22static void enable_pciasic_irq(unsigned int irq)
23{
24 unsigned int mask = 1 << (irq - PCIMT_IRQ_INT2);
25 unsigned long flags;
26
27 spin_lock_irqsave(&pciasic_lock, flags);
28 *(volatile u8 *) PCIMT_IRQSEL |= mask;
29 spin_unlock_irqrestore(&pciasic_lock, flags);

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64 .ack = mask_and_ack_pciasic_irq,
65 .end = end_pciasic_irq,
66};
67
68/*
69 * hwint0 should deal with MP agent, ASIC PCI, EISA NMI and debug
70 * button interrupts. Later ...
71 */
74void pciasic_hwint0(struct pt_regs *regs)
72static void pciasic_hwint0(struct pt_regs *regs)
75{
76 panic("Received int0 but no handler yet ...");
77}
78
79/* This interrupt was used for the com1 console on the first prototypes. */
73{
74 panic("Received int0 but no handler yet ...");
75}
76
77/* This interrupt was used for the com1 console on the first prototypes. */
80void pciasic_hwint2(struct pt_regs *regs)
78static void pciasic_hwint2(struct pt_regs *regs)
81{
82 /* I think this shouldn't happen on production machines. */
83 panic("hwint2 and no handler yet");
84}
85
86/* hwint5 is the r4k count / compare interrupt */
79{
80 /* I think this shouldn't happen on production machines. */
81 panic("hwint2 and no handler yet");
82}
83
84/* hwint5 is the r4k count / compare interrupt */
87void pciasic_hwint5(struct pt_regs *regs)
85static void pciasic_hwint5(struct pt_regs *regs)
88{
89 panic("hwint5 and no handler yet");
90}
91
92static unsigned int ls1bit8(unsigned int x)
93{
94 int b = 7, s;
95

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100 return b;
101}
102
103/*
104 * hwint 1 deals with EISA and SCSI interrupts,
105 *
106 * The EISA_INT bit in CSITPEND is high active, all others are low active.
107 */
86{
87 panic("hwint5 and no handler yet");
88}
89
90static unsigned int ls1bit8(unsigned int x)
91{
92 int b = 7, s;
93

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98 return b;
99}
100
101/*
102 * hwint 1 deals with EISA and SCSI interrupts,
103 *
104 * The EISA_INT bit in CSITPEND is high active, all others are low active.
105 */
108void pciasic_hwint1(struct pt_regs *regs)
106static void pciasic_hwint1(struct pt_regs *regs)
109{
110 u8 pend = *(volatile char *)PCIMT_CSITPEND;
111 unsigned long flags;
112
113 if (pend & IT_EISA) {
114 int irq;
115 /*
116 * Note: ASIC PCI's builtin interrupt achknowledge feature is

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130 do_IRQ(PCIMT_IRQ_SCSI, regs);
131 write_c0_status(flags);
132 }
133}
134
135/*
136 * hwint 3 should deal with the PCI A - D interrupts,
137 */
107{
108 u8 pend = *(volatile char *)PCIMT_CSITPEND;
109 unsigned long flags;
110
111 if (pend & IT_EISA) {
112 int irq;
113 /*
114 * Note: ASIC PCI's builtin interrupt achknowledge feature is

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128 do_IRQ(PCIMT_IRQ_SCSI, regs);
129 write_c0_status(flags);
130 }
131}
132
133/*
134 * hwint 3 should deal with the PCI A - D interrupts,
135 */
138void pciasic_hwint3(struct pt_regs *regs)
136static void pciasic_hwint3(struct pt_regs *regs)
139{
140 u8 pend = *(volatile char *)PCIMT_CSITPEND;
141 int irq;
142
143 pend &= (IT_INTA | IT_INTB | IT_INTC | IT_INTD);
144 clear_c0_status(IE_IRQ3);
145 irq = PCIMT_IRQ_INT2 + ls1bit8(pend);
146 do_IRQ(irq, regs);
147 set_c0_status(IE_IRQ3);
148}
149
150/*
151 * hwint 4 is used for only the onboard PCnet 32.
152 */
137{
138 u8 pend = *(volatile char *)PCIMT_CSITPEND;
139 int irq;
140
141 pend &= (IT_INTA | IT_INTB | IT_INTC | IT_INTD);
142 clear_c0_status(IE_IRQ3);
143 irq = PCIMT_IRQ_INT2 + ls1bit8(pend);
144 do_IRQ(irq, regs);
145 set_c0_status(IE_IRQ3);
146}
147
148/*
149 * hwint 4 is used for only the onboard PCnet 32.
150 */
153void pciasic_hwint4(struct pt_regs *regs)
151static void pciasic_hwint4(struct pt_regs *regs)
154{
155 clear_c0_status(IE_IRQ4);
156 do_IRQ(PCIMT_IRQ_ETHERNET, regs);
157 set_c0_status(IE_IRQ4);
158}
159
152{
153 clear_c0_status(IE_IRQ4);
154 do_IRQ(PCIMT_IRQ_ETHERNET, regs);
155 set_c0_status(IE_IRQ4);
156}
157
158asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
159{
160 unsigned int pending = read_c0_status() & read_c0_cause();
161 static unsigned char led_cache;
162
163 *(volatile unsigned char *) PCIMT_CSLED = ++led_cache;
164
165 if (pending & 0x0800)
166 pciasic_hwint1(regs);
167 else if (pending & 0x4000)
168 pciasic_hwint4(regs);
169 else if (pending & 0x2000)
170 pciasic_hwint3(regs);
171 else if (pending & 0x1000)
172 pciasic_hwint2(regs);
173 else if (pending & 0x8000)
174 pciasic_hwint5(regs);
175 else if (pending & 0x0400)
176 pciasic_hwint0(regs);
177}
178
160void __init init_pciasic(void)
161{
162 unsigned long flags;
163
164 spin_lock_irqsave(&pciasic_lock, flags);
165 * (volatile u8 *) PCIMT_IRQSEL =
166 IT_EISA | IT_INTA | IT_INTB | IT_INTC | IT_INTD;
167 spin_unlock_irqrestore(&pciasic_lock, flags);
168}
169
170/*
171 * On systems with i8259-style interrupt controllers we assume for
172 * driver compatibility reasons interrupts 0 - 15 to be the i8295
173 * interrupts even if the hardware uses a different interrupt numbering.
174 */
175void __init arch_init_irq(void)
176{
177 int i;
178
179void __init init_pciasic(void)
180{
181 unsigned long flags;
182
183 spin_lock_irqsave(&pciasic_lock, flags);
184 * (volatile u8 *) PCIMT_IRQSEL =
185 IT_EISA | IT_INTA | IT_INTB | IT_INTC | IT_INTD;
186 spin_unlock_irqrestore(&pciasic_lock, flags);
187}
188
189/*
190 * On systems with i8259-style interrupt controllers we assume for
191 * driver compatibility reasons interrupts 0 - 15 to be the i8295
192 * interrupts even if the hardware uses a different interrupt numbering.
193 */
194void __init arch_init_irq(void)
195{
196 int i;
197
179 set_except_vector(0, sni_rm200_pci_handle_int);
180
181 init_i8259_irqs(); /* Integrated i8259 */
182 init_pciasic();
183
184 /* Actually we've got more interrupts to handle ... */
185 for (i = PCIMT_IRQ_INT2; i <= PCIMT_IRQ_ETHERNET; i++) {
186 irq_desc[i].status = IRQ_DISABLED;
187 irq_desc[i].action = 0;
188 irq_desc[i].depth = 1;
189 irq_desc[i].handler = &pciasic_irq_type;
190 }
191
192 change_c0_status(ST0_IM, IE_IRQ1|IE_IRQ2|IE_IRQ3|IE_IRQ4);
193}
198 init_i8259_irqs(); /* Integrated i8259 */
199 init_pciasic();
200
201 /* Actually we've got more interrupts to handle ... */
202 for (i = PCIMT_IRQ_INT2; i <= PCIMT_IRQ_ETHERNET; i++) {
203 irq_desc[i].status = IRQ_DISABLED;
204 irq_desc[i].action = 0;
205 irq_desc[i].depth = 1;
206 irq_desc[i].handler = &pciasic_irq_type;
207 }
208
209 change_c0_status(ST0_IM, IE_IRQ1|IE_IRQ2|IE_IRQ3|IE_IRQ4);
210}