uasm.c (f838bad1b3be8ca0c785ee0e0c570dfda74cf377) uasm.c (fb2a27e743cd565c25cd896911e494482a8b7251)
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * A small micro-assembler. It is intentionally kept simple, does only
7 * support a subset of instructions, and does not try to hide pipeline
8 * effects like branch delay slots.

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53#define FUNC_SH 0
54#define SET_MASK 0x7
55#define SET_SH 0
56
57enum opcode {
58 insn_invalid,
59 insn_addu, insn_addiu, insn_and, insn_andi, insn_beq,
60 insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl,
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * A small micro-assembler. It is intentionally kept simple, does only
7 * support a subset of instructions, and does not try to hide pipeline
8 * effects like branch delay slots.

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53#define FUNC_SH 0
54#define SET_MASK 0x7
55#define SET_SH 0
56
57enum opcode {
58 insn_invalid,
59 insn_addu, insn_addiu, insn_and, insn_andi, insn_beq,
60 insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl,
61 insn_bne, insn_daddu, insn_daddiu, insn_dmfc0, insn_dmtc0,
62 insn_dsll, insn_dsll32, insn_dsra, insn_dsrl, insn_dsrl32,
63 insn_dsubu, insn_eret, insn_j, insn_jal, insn_jr, insn_ld,
64 insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0, insn_mtc0,
65 insn_ori, insn_rfe, insn_sc, insn_scd, insn_sd, insn_sll,
66 insn_sra, insn_srl, insn_subu, insn_sw, insn_tlbp, insn_tlbwi,
67 insn_tlbwr, insn_xor, insn_xori
61 insn_bne, insn_cache, insn_daddu, insn_daddiu, insn_dmfc0,
62 insn_dmtc0, insn_dsll, insn_dsll32, insn_dsra, insn_dsrl,
63 insn_dsrl32, insn_dsubu, insn_eret, insn_j, insn_jal, insn_jr,
64 insn_ld, insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0,
65 insn_mtc0, insn_ori, insn_pref, insn_rfe, insn_sc, insn_scd,
66 insn_sd, insn_sll, insn_sra, insn_srl, insn_subu, insn_sw,
67 insn_tlbp, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori
68};
69
70struct insn {
71 enum opcode opcode;
72 u32 match;
73 enum fields fields;
74};
75

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89 { insn_andi, M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
90 { insn_beq, M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
91 { insn_beql, M(beql_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
92 { insn_bgez, M(bcond_op, 0, bgez_op, 0, 0, 0), RS | BIMM },
93 { insn_bgezl, M(bcond_op, 0, bgezl_op, 0, 0, 0), RS | BIMM },
94 { insn_bltz, M(bcond_op, 0, bltz_op, 0, 0, 0), RS | BIMM },
95 { insn_bltzl, M(bcond_op, 0, bltzl_op, 0, 0, 0), RS | BIMM },
96 { insn_bne, M(bne_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
68};
69
70struct insn {
71 enum opcode opcode;
72 u32 match;
73 enum fields fields;
74};
75

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89 { insn_andi, M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
90 { insn_beq, M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
91 { insn_beql, M(beql_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
92 { insn_bgez, M(bcond_op, 0, bgez_op, 0, 0, 0), RS | BIMM },
93 { insn_bgezl, M(bcond_op, 0, bgezl_op, 0, 0, 0), RS | BIMM },
94 { insn_bltz, M(bcond_op, 0, bltz_op, 0, 0, 0), RS | BIMM },
95 { insn_bltzl, M(bcond_op, 0, bltzl_op, 0, 0, 0), RS | BIMM },
96 { insn_bne, M(bne_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
97 { insn_cache, M(cache_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
97 { insn_daddiu, M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
98 { insn_daddu, M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD },
99 { insn_dmfc0, M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET},
100 { insn_dmtc0, M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET},
101 { insn_dsll, M(spec_op, 0, 0, 0, 0, dsll_op), RT | RD | RE },
102 { insn_dsll32, M(spec_op, 0, 0, 0, 0, dsll32_op), RT | RD | RE },
103 { insn_dsra, M(spec_op, 0, 0, 0, 0, dsra_op), RT | RD | RE },
104 { insn_dsrl, M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE },

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111 { insn_ld, M(ld_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
112 { insn_ll, M(ll_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
113 { insn_lld, M(lld_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
114 { insn_lui, M(lui_op, 0, 0, 0, 0, 0), RT | SIMM },
115 { insn_lw, M(lw_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
116 { insn_mfc0, M(cop0_op, mfc_op, 0, 0, 0, 0), RT | RD | SET},
117 { insn_mtc0, M(cop0_op, mtc_op, 0, 0, 0, 0), RT | RD | SET},
118 { insn_ori, M(ori_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
98 { insn_daddiu, M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
99 { insn_daddu, M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD },
100 { insn_dmfc0, M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET},
101 { insn_dmtc0, M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET},
102 { insn_dsll, M(spec_op, 0, 0, 0, 0, dsll_op), RT | RD | RE },
103 { insn_dsll32, M(spec_op, 0, 0, 0, 0, dsll32_op), RT | RD | RE },
104 { insn_dsra, M(spec_op, 0, 0, 0, 0, dsra_op), RT | RD | RE },
105 { insn_dsrl, M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE },

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112 { insn_ld, M(ld_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
113 { insn_ll, M(ll_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
114 { insn_lld, M(lld_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
115 { insn_lui, M(lui_op, 0, 0, 0, 0, 0), RT | SIMM },
116 { insn_lw, M(lw_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
117 { insn_mfc0, M(cop0_op, mfc_op, 0, 0, 0, 0), RT | RD | SET},
118 { insn_mtc0, M(cop0_op, mtc_op, 0, 0, 0, 0), RT | RD | SET},
119 { insn_ori, M(ori_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
120 { insn_pref, M(pref_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
119 { insn_rfe, M(cop0_op, cop_op, 0, 0, 0, rfe_op), 0 },
120 { insn_sc, M(sc_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
121 { insn_scd, M(scd_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
122 { insn_sd, M(sd_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
123 { insn_sll, M(spec_op, 0, 0, 0, 0, sll_op), RT | RD | RE },
124 { insn_sra, M(spec_op, 0, 0, 0, 0, sra_op), RT | RD | RE },
125 { insn_srl, M(spec_op, 0, 0, 0, 0, srl_op), RT | RD | RE },
126 { insn_subu, M(spec_op, 0, 0, 0, 0, subu_op), RS | RT | RD },

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332I_u3u1u2(_and)
333I_u1u2s3(_beq)
334I_u1u2s3(_beql)
335I_u1s2(_bgez)
336I_u1s2(_bgezl)
337I_u1s2(_bltz)
338I_u1s2(_bltzl)
339I_u1u2s3(_bne)
121 { insn_rfe, M(cop0_op, cop_op, 0, 0, 0, rfe_op), 0 },
122 { insn_sc, M(sc_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
123 { insn_scd, M(scd_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
124 { insn_sd, M(sd_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
125 { insn_sll, M(spec_op, 0, 0, 0, 0, sll_op), RT | RD | RE },
126 { insn_sra, M(spec_op, 0, 0, 0, 0, sra_op), RT | RD | RE },
127 { insn_srl, M(spec_op, 0, 0, 0, 0, srl_op), RT | RD | RE },
128 { insn_subu, M(spec_op, 0, 0, 0, 0, subu_op), RS | RT | RD },

--- 205 unchanged lines hidden (view full) ---

334I_u3u1u2(_and)
335I_u1u2s3(_beq)
336I_u1u2s3(_beql)
337I_u1s2(_bgez)
338I_u1s2(_bgezl)
339I_u1s2(_bltz)
340I_u1s2(_bltzl)
341I_u1u2s3(_bne)
342I_u2s3u1(_cache)
340I_u1u2u3(_dmfc0)
341I_u1u2u3(_dmtc0)
342I_u2u1s3(_daddiu)
343I_u3u1u2(_daddu)
344I_u2u1u3(_dsll)
345I_u2u1u3(_dsll32)
346I_u2u1u3(_dsra)
347I_u2u1u3(_dsrl)

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354I_u2s3u1(_ld)
355I_u2s3u1(_ll)
356I_u2s3u1(_lld)
357I_u1s2(_lui)
358I_u2s3u1(_lw)
359I_u1u2u3(_mfc0)
360I_u1u2u3(_mtc0)
361I_u2u1u3(_ori)
343I_u1u2u3(_dmfc0)
344I_u1u2u3(_dmtc0)
345I_u2u1s3(_daddiu)
346I_u3u1u2(_daddu)
347I_u2u1u3(_dsll)
348I_u2u1u3(_dsll32)
349I_u2u1u3(_dsra)
350I_u2u1u3(_dsrl)

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357I_u2s3u1(_ld)
358I_u2s3u1(_ll)
359I_u2s3u1(_lld)
360I_u1s2(_lui)
361I_u2s3u1(_lw)
362I_u1u2u3(_mfc0)
363I_u1u2u3(_mtc0)
364I_u2u1u3(_ori)
365I_u2s3u1(_pref)
362I_0(_rfe)
363I_u2s3u1(_sc)
364I_u2s3u1(_scd)
365I_u2s3u1(_sd)
366I_u2u1u3(_sll)
367I_u2u1u3(_sra)
368I_u2u1u3(_srl)
369I_u3u1u2(_subu)

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550void __cpuinit
551uasm_il_beqzl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
552{
553 uasm_r_mips_pc16(r, *p, lid);
554 uasm_i_beqzl(p, reg, 0);
555}
556
557void __cpuinit
366I_0(_rfe)
367I_u2s3u1(_sc)
368I_u2s3u1(_scd)
369I_u2s3u1(_sd)
370I_u2u1u3(_sll)
371I_u2u1u3(_sra)
372I_u2u1u3(_srl)
373I_u3u1u2(_subu)

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554void __cpuinit
555uasm_il_beqzl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
556{
557 uasm_r_mips_pc16(r, *p, lid);
558 uasm_i_beqzl(p, reg, 0);
559}
560
561void __cpuinit
562uasm_il_bne(u32 **p, struct uasm_reloc **r, unsigned int reg1,
563 unsigned int reg2, int lid)
564{
565 uasm_r_mips_pc16(r, *p, lid);
566 uasm_i_bne(p, reg1, reg2, 0);
567}
568
569void __cpuinit
558uasm_il_bnez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
559{
560 uasm_r_mips_pc16(r, *p, lid);
561 uasm_i_bnez(p, reg, 0);
562}
563
564void __cpuinit
565uasm_il_bgezl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
566{
567 uasm_r_mips_pc16(r, *p, lid);
568 uasm_i_bgezl(p, reg, 0);
569}
570
571void __cpuinit
572uasm_il_bgez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
573{
574 uasm_r_mips_pc16(r, *p, lid);
575 uasm_i_bgez(p, reg, 0);
576}
570uasm_il_bnez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
571{
572 uasm_r_mips_pc16(r, *p, lid);
573 uasm_i_bnez(p, reg, 0);
574}
575
576void __cpuinit
577uasm_il_bgezl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
578{
579 uasm_r_mips_pc16(r, *p, lid);
580 uasm_i_bgezl(p, reg, 0);
581}
582
583void __cpuinit
584uasm_il_bgez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
585{
586 uasm_r_mips_pc16(r, *p, lid);
587 uasm_i_bgez(p, reg, 0);
588}