page.c (9a64e8e0ace51b309fdcff4b4754b3649250382a) page.c (c022630633624a75b3b58f43dd3c6cc896a56cff)
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003, 04, 05 Ralf Baechle (ralf@linux-mips.org)
7 * Copyright (C) 2007 Maciej W. Rozycki
8 * Copyright (C) 2008 Thiemo Seufer
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003, 04, 05 Ralf Baechle (ralf@linux-mips.org)
7 * Copyright (C) 2007 Maciej W. Rozycki
8 * Copyright (C) 2008 Thiemo Seufer
9 * Copyright (C) 2012 MIPS Technologies, Inc.
9 */
10#include <linux/init.h>
11#include <linux/kernel.h>
12#include <linux/sched.h>
13#include <linux/smp.h>
14#include <linux/mm.h>
15#include <linux/module.h>
16#include <linux/proc_fs.h>

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66
67/* We need one branch and therefore one relocation per target label. */
68static struct uasm_label __cpuinitdata labels[5];
69static struct uasm_reloc __cpuinitdata relocs[5];
70
71#define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x00002010)
72#define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x00002020)
73
10 */
11#include <linux/init.h>
12#include <linux/kernel.h>
13#include <linux/sched.h>
14#include <linux/smp.h>
15#include <linux/mm.h>
16#include <linux/module.h>
17#include <linux/proc_fs.h>

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67
68/* We need one branch and therefore one relocation per target label. */
69static struct uasm_label __cpuinitdata labels[5];
70static struct uasm_reloc __cpuinitdata relocs[5];
71
72#define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x00002010)
73#define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x00002020)
74
74/*
75 * Maximum sizes:
76 *
77 * R4000 128 bytes S-cache: 0x058 bytes
78 * R4600 v1.7: 0x05c bytes
79 * R4600 v2.0: 0x060 bytes
80 * With prefetching, 16 word strides 0x120 bytes
81 */
82
83static u32 clear_page_array[0x120 / 4];
84
85#ifdef CONFIG_SIBYTE_DMA_PAGEOPS
86void clear_page_cpu(void *page) __attribute__((alias("clear_page_array")));
87#else
88void clear_page(void *page) __attribute__((alias("clear_page_array")));
89#endif
90
91EXPORT_SYMBOL(clear_page);
92
93/*
94 * Maximum sizes:
95 *
96 * R4000 128 bytes S-cache: 0x11c bytes
97 * R4600 v1.7: 0x080 bytes
98 * R4600 v2.0: 0x07c bytes
99 * With prefetching, 16 word strides 0x540 bytes
100 */
101static u32 copy_page_array[0x540 / 4];
102
103#ifdef CONFIG_SIBYTE_DMA_PAGEOPS
104void
105copy_page_cpu(void *to, void *from) __attribute__((alias("copy_page_array")));
106#else
107void copy_page(void *to, void *from) __attribute__((alias("copy_page_array")));
108#endif
109
110EXPORT_SYMBOL(copy_page);
111
112
113static int pref_bias_clear_store __cpuinitdata;
114static int pref_bias_copy_load __cpuinitdata;
115static int pref_bias_copy_store __cpuinitdata;
116
117static u32 pref_src_mode __cpuinitdata;
118static u32 pref_dst_mode __cpuinitdata;
119
120static int clear_word_size __cpuinitdata;

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277 if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
278 uasm_i_lw(buf, ZERO, ZERO, AT);
279
280 uasm_i_cache(buf, Create_Dirty_Excl_D, off, A0);
281 }
282 }
283}
284
75static int pref_bias_clear_store __cpuinitdata;
76static int pref_bias_copy_load __cpuinitdata;
77static int pref_bias_copy_store __cpuinitdata;
78
79static u32 pref_src_mode __cpuinitdata;
80static u32 pref_dst_mode __cpuinitdata;
81
82static int clear_word_size __cpuinitdata;

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239 if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
240 uasm_i_lw(buf, ZERO, ZERO, AT);
241
242 uasm_i_cache(buf, Create_Dirty_Excl_D, off, A0);
243 }
244 }
245}
246
247extern u32 __clear_page_start;
248extern u32 __clear_page_end;
249extern u32 __copy_page_start;
250extern u32 __copy_page_end;
251
285void __cpuinit build_clear_page(void)
286{
287 int off;
252void __cpuinit build_clear_page(void)
253{
254 int off;
288 u32 *buf = (u32 *)&clear_page_array;
255 u32 *buf = &__clear_page_start;
289 struct uasm_label *l = labels;
290 struct uasm_reloc *r = relocs;
291 int i;
292
293 memset(labels, 0, sizeof(labels));
294 memset(relocs, 0, sizeof(relocs));
295
296 set_prefetch_parameters();

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351 build_clear_store(&buf, off);
352 off += clear_word_size;
353 } while (off < 0);
354 }
355
356 uasm_i_jr(&buf, RA);
357 uasm_i_nop(&buf);
358
256 struct uasm_label *l = labels;
257 struct uasm_reloc *r = relocs;
258 int i;
259
260 memset(labels, 0, sizeof(labels));
261 memset(relocs, 0, sizeof(relocs));
262
263 set_prefetch_parameters();

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318 build_clear_store(&buf, off);
319 off += clear_word_size;
320 } while (off < 0);
321 }
322
323 uasm_i_jr(&buf, RA);
324 uasm_i_nop(&buf);
325
359 BUG_ON(buf > clear_page_array + ARRAY_SIZE(clear_page_array));
326 BUG_ON(buf > &__clear_page_end);
360
361 uasm_resolve_relocs(relocs, labels);
362
363 pr_debug("Synthesized clear page handler (%u instructions).\n",
327
328 uasm_resolve_relocs(relocs, labels);
329
330 pr_debug("Synthesized clear page handler (%u instructions).\n",
364 (u32)(buf - clear_page_array));
331 (u32)(buf - &__clear_page_start));
365
366 pr_debug("\t.set push\n");
367 pr_debug("\t.set noreorder\n");
332
333 pr_debug("\t.set push\n");
334 pr_debug("\t.set noreorder\n");
368 for (i = 0; i < (buf - clear_page_array); i++)
369 pr_debug("\t.word 0x%08x\n", clear_page_array[i]);
335 for (i = 0; i < (buf - &__clear_page_start); i++)
336 pr_debug("\t.word 0x%08x\n", (&__clear_page_start)[i]);
370 pr_debug("\t.set pop\n");
371}
372
373static void __cpuinit build_copy_load(u32 **buf, int reg, int off)
374{
375 if (cpu_has_64bit_gp_regs) {
376 uasm_i_ld(buf, reg, off, A1);
377 } else {

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422 uasm_i_cache(buf, Create_Dirty_Excl_D, off, A0);
423 }
424 }
425}
426
427void __cpuinit build_copy_page(void)
428{
429 int off;
337 pr_debug("\t.set pop\n");
338}
339
340static void __cpuinit build_copy_load(u32 **buf, int reg, int off)
341{
342 if (cpu_has_64bit_gp_regs) {
343 uasm_i_ld(buf, reg, off, A1);
344 } else {

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389 uasm_i_cache(buf, Create_Dirty_Excl_D, off, A0);
390 }
391 }
392}
393
394void __cpuinit build_copy_page(void)
395{
396 int off;
430 u32 *buf = (u32 *)&copy_page_array;
397 u32 *buf = &__copy_page_start;
431 struct uasm_label *l = labels;
432 struct uasm_reloc *r = relocs;
433 int i;
434
435 memset(labels, 0, sizeof(labels));
436 memset(relocs, 0, sizeof(relocs));
437
438 set_prefetch_parameters();

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590 build_copy_store(&buf, T3, off + 3 * copy_word_size);
591 off += 4 * copy_word_size;
592 } while (off < 0);
593 }
594
595 uasm_i_jr(&buf, RA);
596 uasm_i_nop(&buf);
597
398 struct uasm_label *l = labels;
399 struct uasm_reloc *r = relocs;
400 int i;
401
402 memset(labels, 0, sizeof(labels));
403 memset(relocs, 0, sizeof(relocs));
404
405 set_prefetch_parameters();

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557 build_copy_store(&buf, T3, off + 3 * copy_word_size);
558 off += 4 * copy_word_size;
559 } while (off < 0);
560 }
561
562 uasm_i_jr(&buf, RA);
563 uasm_i_nop(&buf);
564
598 BUG_ON(buf > copy_page_array + ARRAY_SIZE(copy_page_array));
565 BUG_ON(buf > &__copy_page_end);
599
600 uasm_resolve_relocs(relocs, labels);
601
602 pr_debug("Synthesized copy page handler (%u instructions).\n",
566
567 uasm_resolve_relocs(relocs, labels);
568
569 pr_debug("Synthesized copy page handler (%u instructions).\n",
603 (u32)(buf - copy_page_array));
570 (u32)(buf - &__copy_page_start));
604
605 pr_debug("\t.set push\n");
606 pr_debug("\t.set noreorder\n");
571
572 pr_debug("\t.set push\n");
573 pr_debug("\t.set noreorder\n");
607 for (i = 0; i < (buf - copy_page_array); i++)
608 pr_debug("\t.word 0x%08x\n", copy_page_array[i]);
574 for (i = 0; i < (buf - &__copy_page_start); i++)
575 pr_debug("\t.word 0x%08x\n", (&__copy_page_start)[i]);
609 pr_debug("\t.set pop\n");
610}
611
612#ifdef CONFIG_SIBYTE_DMA_PAGEOPS
576 pr_debug("\t.set pop\n");
577}
578
579#ifdef CONFIG_SIBYTE_DMA_PAGEOPS
580extern void clear_page_cpu(void *page);
581extern void copy_page_cpu(void *to, void *from);
613
614/*
615 * Pad descriptors to cacheline, since each is exclusively owned by a
616 * particular CPU.
617 */
618struct dmadscr {
619 u64 dscr_a;
620 u64 dscr_b;

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583/*
584 * Pad descriptors to cacheline, since each is exclusively owned by a
585 * particular CPU.
586 */
587struct dmadscr {
588 u64 dscr_a;
589 u64 dscr_b;

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