c-r4k.c (4854c7b27f0975a2b629f35ea3996d2968eb7c4f) c-r4k.c (9318c51acd9689505850152cc98277a6d6f2d752)
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
7 * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org)
8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.

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1087 c->scache.ways = 1;
1088 c->dcache.waybit = 0; /* does not matter */
1089
1090 return 1;
1091}
1092
1093extern int r5k_sc_init(void);
1094extern int rm7k_sc_init(void);
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
7 * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org)
8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.

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1087 c->scache.ways = 1;
1088 c->dcache.waybit = 0; /* does not matter */
1089
1090 return 1;
1091}
1092
1093extern int r5k_sc_init(void);
1094extern int rm7k_sc_init(void);
1095extern int mips_sc_init(void);
1095
1096static void __init setup_scache(void)
1097{
1098 struct cpuinfo_mips *c = &current_cpu_data;
1099 unsigned int config = read_c0_config();
1100 int sc_present = 0;
1101
1102 /*

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1134 case CPU_RM7000:
1135 case CPU_RM9000:
1136#ifdef CONFIG_RM7000_CPU_SCACHE
1137 rm7k_sc_init();
1138#endif
1139 return;
1140
1141 default:
1096
1097static void __init setup_scache(void)
1098{
1099 struct cpuinfo_mips *c = &current_cpu_data;
1100 unsigned int config = read_c0_config();
1101 int sc_present = 0;
1102
1103 /*

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1135 case CPU_RM7000:
1136 case CPU_RM9000:
1137#ifdef CONFIG_RM7000_CPU_SCACHE
1138 rm7k_sc_init();
1139#endif
1140 return;
1141
1142 default:
1143 if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
1144 c->isa_level == MIPS_CPU_ISA_M32R2 ||
1145 c->isa_level == MIPS_CPU_ISA_M64R1 ||
1146 c->isa_level == MIPS_CPU_ISA_M64R2) {
1147#ifdef CONFIG_MIPS_CPU_SCACHE
1148 if (mips_sc_init ()) {
1149 scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
1150 printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n",
1151 scache_size >> 10,
1152 way_string[c->scache.ways], c->scache.linesz);
1153 }
1154#else
1155 if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
1156 panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
1157#endif
1158 return;
1159 }
1142 sc_present = 0;
1143 }
1144
1145 if (!sc_present)
1146 return;
1147
1160 sc_present = 0;
1161 }
1162
1163 if (!sc_present)
1164 return;
1165
1148 if ((c->isa_level == MIPS_CPU_ISA_M32R1 ||
1149 c->isa_level == MIPS_CPU_ISA_M64R1) &&
1150 !(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
1151 panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
1152
1153 /* compute a couple of other cache variables */
1154 c->scache.waysize = scache_size / c->scache.ways;
1155
1156 c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
1157
1158 printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1159 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1160

--- 116 unchanged lines hidden --- 		1166 /* compute a couple of other cache variables */
1167 c->scache.waysize = scache_size / c->scache.ways;
1168
1169 c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
1170
1171 printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1172 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1173

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