c-r4k.c (351336929ccf222ae38ff0cb7a8dd5fd5c6236a0) c-r4k.c (39b8d5254246ac56342b72f812255c8f7a74dca9)
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
7 * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org)
8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.

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49
50#if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC)
51 smp_call_function(func, info, retry, wait);
52#endif
53 func(info);
54 preempt_enable();
55}
56
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
7 * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org)
8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.

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49
50#if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC)
51 smp_call_function(func, info, retry, wait);
52#endif
53 func(info);
54 preempt_enable();
55}
56
57#if defined(CONFIG_MIPS_CMP)
58#define cpu_has_safe_index_cacheops 0
59#else
60#define cpu_has_safe_index_cacheops 1
61#endif
62
57/*
58 * Must die.
59 */
60static unsigned long icache_size __read_mostly;
61static unsigned long dcache_size __read_mostly;
62static unsigned long scache_size __read_mostly;
63
64/*

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477 vaddr = kmap_coherent(page, addr);
478 else
479 vaddr = kmap_atomic(page, KM_USER0);
480 addr = (unsigned long)vaddr;
481 }
482
483 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
484 r4k_blast_dcache_page(addr);
63/*
64 * Must die.
65 */
66static unsigned long icache_size __read_mostly;
67static unsigned long dcache_size __read_mostly;
68static unsigned long scache_size __read_mostly;
69
70/*

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483 vaddr = kmap_coherent(page, addr);
484 else
485 vaddr = kmap_atomic(page, KM_USER0);
486 addr = (unsigned long)vaddr;
487 }
488
489 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
490 r4k_blast_dcache_page(addr);
491 if (exec && !cpu_icache_snoops_remote_store)
492 r4k_blast_scache_page(addr);
485 }
486 if (exec) {
487 if (vaddr && cpu_has_vtag_icache && mm == current->active_mm) {
488 int cpu = smp_processor_id();
489
490 if (cpu_context(cpu, mm) != 0)
491 drop_mmu_context(mm, cpu);
492 } else

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579 return;
580 }
581
582 /*
583 * Either no secondary cache or the available caches don't have the
584 * subset property so we have to flush the primary caches
585 * explicitly
586 */
493 }
494 if (exec) {
495 if (vaddr && cpu_has_vtag_icache && mm == current->active_mm) {
496 int cpu = smp_processor_id();
497
498 if (cpu_context(cpu, mm) != 0)
499 drop_mmu_context(mm, cpu);
500 } else

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587 return;
588 }
589
590 /*
591 * Either no secondary cache or the available caches don't have the
592 * subset property so we have to flush the primary caches
593 * explicitly
594 */
587 if (size >= dcache_size) {
595 if (cpu_has_safe_index_cacheops && size >= dcache_size) {
588 r4k_blast_dcache();
589 } else {
590 R4600_HIT_CACHEOP_WAR_IMPL;
591 blast_dcache_range(addr, addr + size);
592 }
593
594 bc_wback_inv(addr, size);
595}

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602 if (cpu_has_inclusive_pcaches) {
603 if (size >= scache_size)
604 r4k_blast_scache();
605 else
606 blast_inv_scache_range(addr, addr + size);
607 return;
608 }
609
596 r4k_blast_dcache();
597 } else {
598 R4600_HIT_CACHEOP_WAR_IMPL;
599 blast_dcache_range(addr, addr + size);
600 }
601
602 bc_wback_inv(addr, size);
603}

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610 if (cpu_has_inclusive_pcaches) {
611 if (size >= scache_size)
612 r4k_blast_scache();
613 else
614 blast_inv_scache_range(addr, addr + size);
615 return;
616 }
617
610 if (size >= dcache_size) {
618 if (cpu_has_safe_index_cacheops && size >= dcache_size) {
611 r4k_blast_dcache();
612 } else {
613 R4600_HIT_CACHEOP_WAR_IMPL;
614 blast_inv_dcache_range(addr, addr + size);
615 }
616
617 bc_inv(addr, size);
618}

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964 case CPU_R10000:
965 case CPU_R12000:
966 case CPU_R14000:
967 break;
968
969 case CPU_24K:
970 case CPU_34K:
971 case CPU_74K:
619 r4k_blast_dcache();
620 } else {
621 R4600_HIT_CACHEOP_WAR_IMPL;
622 blast_inv_dcache_range(addr, addr + size);
623 }
624
625 bc_inv(addr, size);
626}

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972 case CPU_R10000:
973 case CPU_R12000:
974 case CPU_R14000:
975 break;
976
977 case CPU_24K:
978 case CPU_34K:
979 case CPU_74K:
980 case CPU_1004K:
972 if ((read_c0_config7() & (1 << 16))) {
973 /* effectively physically indexed dcache,
974 thus no virtual aliases. */
975 c->dcache.flags |= MIPS_CACHE_PINDEX;
976 break;
977 }
978 default:
979 if (c->dcache.waysize > PAGE_SIZE)

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1260 case CPU_AU1000: /* rev. DA, HA, HB */
1261 case CPU_AU1100: /* rev. AB, BA, BC ?? */
1262 case CPU_AU1500: /* rev. AB */
1263 au1x00_fixup_config_od();
1264 break;
1265 }
1266}
1267
981 if ((read_c0_config7() & (1 << 16))) {
982 /* effectively physically indexed dcache,
983 thus no virtual aliases. */
984 c->dcache.flags |= MIPS_CACHE_PINDEX;
985 break;
986 }
987 default:
988 if (c->dcache.waysize > PAGE_SIZE)

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1269 case CPU_AU1000: /* rev. DA, HA, HB */
1270 case CPU_AU1100: /* rev. AB, BA, BC ?? */
1271 case CPU_AU1500: /* rev. AB */
1272 au1x00_fixup_config_od();
1273 break;
1274 }
1275}
1276
1277#if defined(CONFIG_DMA_NONCOHERENT)
1278
1279static int __cpuinitdata coherentio;
1280
1281static int __init setcoherentio(char *str)
1282{
1283 coherentio = 1;
1284
1285 return 1;
1286}
1287
1288__setup("coherentio", setcoherentio);
1289#endif
1290
1268void __cpuinit r4k_cache_init(void)
1269{
1270 extern void build_clear_page(void);
1271 extern void build_copy_page(void);
1272 extern char __weak except_vec2_generic;
1273 extern char __weak except_vec2_sb1;
1274 struct cpuinfo_mips *c = &current_cpu_data;
1275

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1319 flush_cache_range = r4k_flush_cache_range;
1320
1321 flush_cache_sigtramp = r4k_flush_cache_sigtramp;
1322 flush_icache_all = r4k_flush_icache_all;
1323 local_flush_data_cache_page = local_r4k_flush_data_cache_page;
1324 flush_data_cache_page = r4k_flush_data_cache_page;
1325 flush_icache_range = r4k_flush_icache_range;
1326
1291void __cpuinit r4k_cache_init(void)
1292{
1293 extern void build_clear_page(void);
1294 extern void build_copy_page(void);
1295 extern char __weak except_vec2_generic;
1296 extern char __weak except_vec2_sb1;
1297 struct cpuinfo_mips *c = &current_cpu_data;
1298

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1342 flush_cache_range = r4k_flush_cache_range;
1343
1344 flush_cache_sigtramp = r4k_flush_cache_sigtramp;
1345 flush_icache_all = r4k_flush_icache_all;
1346 local_flush_data_cache_page = local_r4k_flush_data_cache_page;
1347 flush_data_cache_page = r4k_flush_data_cache_page;
1348 flush_icache_range = r4k_flush_icache_range;
1349
1327#ifdef CONFIG_DMA_NONCOHERENT
1328 _dma_cache_wback_inv = r4k_dma_cache_wback_inv;
1329 _dma_cache_wback = r4k_dma_cache_wback_inv;
1330 _dma_cache_inv = r4k_dma_cache_inv;
1350#if defined(CONFIG_DMA_NONCOHERENT)
1351 if (coherentio) {
1352 _dma_cache_wback_inv = (void *)cache_noop;
1353 _dma_cache_wback = (void *)cache_noop;
1354 _dma_cache_inv = (void *)cache_noop;
1355 } else {
1356 _dma_cache_wback_inv = r4k_dma_cache_wback_inv;
1357 _dma_cache_wback = r4k_dma_cache_wback_inv;
1358 _dma_cache_inv = r4k_dma_cache_inv;
1359 }
1331#endif
1332
1333 build_clear_page();
1334 build_copy_page();
1360#endif
1361
1362 build_clear_page();
1363 build_copy_page();
1364#if !defined(CONFIG_MIPS_CMP)
1335 local_r4k___flush_cache_all(NULL);
1365 local_r4k___flush_cache_all(NULL);
1366#endif
1336 coherency_setup();
1337}
1367 coherency_setup();
1368}