| cp1emu.c (f8c3c6717a7128f9601b20f890d658283d59561a) | cp1emu.c (67613f02788d73541c7c9b1c851061b8c223057b) |
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| 1/* 2 * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator 3 * 4 * MIPS floating point support 5 * Copyright (C) 1994-2000 Algorithmics Ltd. 6 * 7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 8 * Copyright (C) 2000 MIPS Technologies, Inc. --- 1729 unchanged lines hidden (view full) --- 1738 if (!cpu_has_mips_4_5_r) 1739 return SIGILL; 1740 1741 if (xcp->regs[MIPSInst_FT(ir)] == 0) 1742 return 0; 1743 SPFROMREG(rv.s, MIPSInst_FS(ir)); 1744 break; 1745 | 1/* 2 * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator 3 * 4 * MIPS floating point support 5 * Copyright (C) 1994-2000 Algorithmics Ltd. 6 * 7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 8 * Copyright (C) 2000 MIPS Technologies, Inc. --- 1729 unchanged lines hidden (view full) --- 1738 if (!cpu_has_mips_4_5_r) 1739 return SIGILL; 1740 1741 if (xcp->regs[MIPSInst_FT(ir)] == 0) 1742 return 0; 1743 SPFROMREG(rv.s, MIPSInst_FS(ir)); 1744 break; 1745 |
| 1746 case fseleqz_op: 1747 if (!cpu_has_mips_r6) 1748 return SIGILL; 1749 1750 SPFROMREG(rv.s, MIPSInst_FT(ir)); 1751 if (rv.w & 0x1) 1752 rv.w = 0; 1753 else 1754 SPFROMREG(rv.s, MIPSInst_FS(ir)); 1755 break; 1756 |
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| 1746 case fabs_op: 1747 handler.u = ieee754sp_abs; 1748 goto scopuop; 1749 1750 case fneg_op: 1751 handler.u = ieee754sp_neg; 1752 goto scopuop; 1753 --- 181 unchanged lines hidden (view full) --- 1935 case fmovn_op: 1936 if (!cpu_has_mips_4_5_r) 1937 return SIGILL; 1938 1939 if (xcp->regs[MIPSInst_FT(ir)] == 0) 1940 return 0; 1941 DPFROMREG(rv.d, MIPSInst_FS(ir)); 1942 break; | 1757 case fabs_op: 1758 handler.u = ieee754sp_abs; 1759 goto scopuop; 1760 1761 case fneg_op: 1762 handler.u = ieee754sp_neg; 1763 goto scopuop; 1764 --- 181 unchanged lines hidden (view full) --- 1946 case fmovn_op: 1947 if (!cpu_has_mips_4_5_r) 1948 return SIGILL; 1949 1950 if (xcp->regs[MIPSInst_FT(ir)] == 0) 1951 return 0; 1952 DPFROMREG(rv.d, MIPSInst_FS(ir)); 1953 break; |
| 1954 1955 case fseleqz_op: 1956 if (!cpu_has_mips_r6) 1957 return SIGILL; 1958 1959 DPFROMREG(rv.d, MIPSInst_FT(ir)); 1960 if (rv.l & 0x1) 1961 rv.l = 0; 1962 else 1963 DPFROMREG(rv.d, MIPSInst_FS(ir)); 1964 break; 1965 |
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| 1943 case fabs_op: 1944 handler.u = ieee754dp_abs; 1945 goto dcopuop; 1946 1947 case fneg_op: 1948 handler.u = ieee754dp_neg; 1949 goto dcopuop; 1950 --- 401 unchanged lines hidden --- | 1966 case fabs_op: 1967 handler.u = ieee754dp_abs; 1968 goto dcopuop; 1969 1970 case fneg_op: 1971 handler.u = ieee754dp_neg; 1972 goto dcopuop; 1973 --- 401 unchanged lines hidden --- |