cp1emu.c (e8f80cc1a6d80587136b015e989a12827e1fcfe5) cp1emu.c (c909ca718e8f50cf484ef06a8dd935e738e8e53d)
1/*
2 * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator
3 *
4 * MIPS floating point support
5 * Copyright (C) 1994-2000 Algorithmics Ltd.
6 *
7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
8 * Copyright (C) 2000 MIPS Technologies, Inc.

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1176 case ctc_op:
1177 /* copregister rd <- rt */
1178 cop1_ctc(xcp, ctx, ir);
1179 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1180 return SIGFPE;
1181 }
1182 break;
1183
1/*
2 * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator
3 *
4 * MIPS floating point support
5 * Copyright (C) 1994-2000 Algorithmics Ltd.
6 *
7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
8 * Copyright (C) 2000 MIPS Technologies, Inc.

--- 1167 unchanged lines hidden (view full) ---

1176 case ctc_op:
1177 /* copregister rd <- rt */
1178 cop1_ctc(xcp, ctx, ir);
1179 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1180 return SIGFPE;
1181 }
1182 break;
1183
1184 case bc1eqz_op:
1185 case bc1nez_op:
1186 if (!cpu_has_mips_r6 || delay_slot(xcp))
1187 return SIGILL;
1188
1189 cond = likely = 0;
1190 switch (MIPSInst_RS(ir)) {
1191 case bc1eqz_op:
1192 if (get_fpr32(&current->thread.fpu.fpr[MIPSInst_RT(ir)], 0) & 0x1)
1193 cond = 1;
1194 break;
1195 case bc1nez_op:
1196 if (!(get_fpr32(&current->thread.fpu.fpr[MIPSInst_RT(ir)], 0) & 0x1))
1197 cond = 1;
1198 break;
1199 }
1200 goto branch_common;
1201
1184 case bc_op:
1185 if (delay_slot(xcp))
1186 return SIGILL;
1187
1188 if (cpu_has_mips_4_5_r)
1189 cbit = fpucondbit[MIPSInst_RT(ir) >> 2];
1190 else
1191 cbit = FPU_CSR_COND;

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1202 break;
1203 case bctl_op:
1204 if (cpu_has_mips_2_3_4_5_r)
1205 likely = 1;
1206 /* Fall through */
1207 case bct_op:
1208 break;
1209 }
1202 case bc_op:
1203 if (delay_slot(xcp))
1204 return SIGILL;
1205
1206 if (cpu_has_mips_4_5_r)
1207 cbit = fpucondbit[MIPSInst_RT(ir) >> 2];
1208 else
1209 cbit = FPU_CSR_COND;

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1220 break;
1221 case bctl_op:
1222 if (cpu_has_mips_2_3_4_5_r)
1223 likely = 1;
1224 /* Fall through */
1225 case bct_op:
1226 break;
1227 }
1210
1228branch_common:
1211 set_delay_slot(xcp);
1212 if (cond) {
1213 /*
1214 * Branch taken: emulate dslot instruction
1215 */
1216 unsigned long bcpc;
1217
1218 /*

--- 1003 unchanged lines hidden --- 		1229 set_delay_slot(xcp);
1230 if (cond) {
1231 /*
1232 * Branch taken: emulate dslot instruction
1233 */
1234 unsigned long bcpc;
1235
1236 /*

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