cp1emu.c (e24c3bec3e8e254a3784b3e4c97bd3a76fbcc807) cp1emu.c (83d43305a1df2aa2976e3ccf012e4cf0dc29673d)
1/*
2 * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator
3 *
4 * MIPS floating point support
5 * Copyright (C) 1994-2000 Algorithmics Ltd.
6 *
7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
8 * Copyright (C) 2000 MIPS Technologies, Inc.

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1773
1774 SPFROMREG(ft, MIPSInst_FT(ir));
1775 SPFROMREG(fs, MIPSInst_FS(ir));
1776 SPFROMREG(fd, MIPSInst_FD(ir));
1777 rv.s = ieee754sp_maddf(fd, fs, ft);
1778 break;
1779 }
1780
1/*
2 * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator
3 *
4 * MIPS floating point support
5 * Copyright (C) 1994-2000 Algorithmics Ltd.
6 *
7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
8 * Copyright (C) 2000 MIPS Technologies, Inc.

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1773
1774 SPFROMREG(ft, MIPSInst_FT(ir));
1775 SPFROMREG(fs, MIPSInst_FS(ir));
1776 SPFROMREG(fd, MIPSInst_FD(ir));
1777 rv.s = ieee754sp_maddf(fd, fs, ft);
1778 break;
1779 }
1780
1781 case fmsubf_op: {
1782 union ieee754sp ft, fs, fd;
1783
1784 if (!cpu_has_mips_r6)
1785 return SIGILL;
1786
1787 SPFROMREG(ft, MIPSInst_FT(ir));
1788 SPFROMREG(fs, MIPSInst_FS(ir));
1789 SPFROMREG(fd, MIPSInst_FD(ir));
1790 rv.s = ieee754sp_msubf(fd, fs, ft);
1791 break;
1792 }
1793
1781 case fabs_op:
1782 handler.u = ieee754sp_abs;
1783 goto scopuop;
1784
1785 case fneg_op:
1786 handler.u = ieee754sp_neg;
1787 goto scopuop;
1788

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2006
2007 DPFROMREG(ft, MIPSInst_FT(ir));
2008 DPFROMREG(fs, MIPSInst_FS(ir));
2009 DPFROMREG(fd, MIPSInst_FD(ir));
2010 rv.d = ieee754dp_maddf(fd, fs, ft);
2011 break;
2012 }
2013
1794 case fabs_op:
1795 handler.u = ieee754sp_abs;
1796 goto scopuop;
1797
1798 case fneg_op:
1799 handler.u = ieee754sp_neg;
1800 goto scopuop;
1801

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2019
2020 DPFROMREG(ft, MIPSInst_FT(ir));
2021 DPFROMREG(fs, MIPSInst_FS(ir));
2022 DPFROMREG(fd, MIPSInst_FD(ir));
2023 rv.d = ieee754dp_maddf(fd, fs, ft);
2024 break;
2025 }
2026
2027 case fmsubf_op: {
2028 union ieee754dp ft, fs, fd;
2029
2030 if (!cpu_has_mips_r6)
2031 return SIGILL;
2032
2033 DPFROMREG(ft, MIPSInst_FT(ir));
2034 DPFROMREG(fs, MIPSInst_FS(ir));
2035 DPFROMREG(fd, MIPSInst_FD(ir));
2036 rv.d = ieee754dp_msubf(fd, fs, ft);
2037 break;
2038 }
2039
2014 case fabs_op:
2015 handler.u = ieee754dp_abs;
2016 goto dcopuop;
2017
2018 case fneg_op:
2019 handler.u = ieee754dp_neg;
2020 goto dcopuop;
2021

--- 401 unchanged lines hidden --- 		2040 case fabs_op:
2041 handler.u = ieee754dp_abs;
2042 goto dcopuop;
2043
2044 case fneg_op:
2045 handler.u = ieee754dp_neg;
2046 goto dcopuop;
2047

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