cp1emu.c (ae5f3f5b81dd2c776f0ad49d6d121ce1255b35eb) cp1emu.c (454854ace22f5a9fdd369a4e428493159a02f029)
1/*
2 * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator
3 *
4 * MIPS floating point support
5 * Copyright (C) 1994-2000 Algorithmics Ltd.
6 *
7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
8 * Copyright (C) 2000 MIPS Technologies, Inc.

--- 1181 unchanged lines hidden (view full) ---

1190 if (!cpu_has_mips_r6 || delay_slot(xcp))
1191 return SIGILL;
1192
1193 cond = likely = 0;
1194 fpr = &current->thread.fpu.fpr[MIPSInst_RT(ir)];
1195 bit0 = get_fpr32(fpr, 0) & 0x1;
1196 switch (MIPSInst_RS(ir)) {
1197 case bc1eqz_op:
1/*
2 * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator
3 *
4 * MIPS floating point support
5 * Copyright (C) 1994-2000 Algorithmics Ltd.
6 *
7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
8 * Copyright (C) 2000 MIPS Technologies, Inc.

--- 1181 unchanged lines hidden (view full) ---

1190 if (!cpu_has_mips_r6 || delay_slot(xcp))
1191 return SIGILL;
1192
1193 cond = likely = 0;
1194 fpr = &current->thread.fpu.fpr[MIPSInst_RT(ir)];
1195 bit0 = get_fpr32(fpr, 0) & 0x1;
1196 switch (MIPSInst_RS(ir)) {
1197 case bc1eqz_op:
1198 MIPS_FPU_EMU_INC_STATS(bc1eqz);
1198 cond = bit0 == 0;
1199 break;
1200 case bc1nez_op:
1199 cond = bit0 == 0;
1200 break;
1201 case bc1nez_op:
1202 MIPS_FPU_EMU_INC_STATS(bc1nez);
1201 cond = bit0 != 0;
1202 break;
1203 }
1204 goto branch_common;
1205
1206 case bc_op:
1207 if (delay_slot(xcp))
1208 return SIGILL;

--- 469 unchanged lines hidden (view full) ---

1678 union ieee754sp(*b) (union ieee754sp, union ieee754sp);
1679 union ieee754sp(*u) (union ieee754sp);
1680 } handler;
1681 union ieee754sp fd, fs, ft;
1682
1683 switch (MIPSInst_FUNC(ir)) {
1684 /* binary ops */
1685 case fadd_op:
1203 cond = bit0 != 0;
1204 break;
1205 }
1206 goto branch_common;
1207
1208 case bc_op:
1209 if (delay_slot(xcp))
1210 return SIGILL;

--- 469 unchanged lines hidden (view full) ---

1680 union ieee754sp(*b) (union ieee754sp, union ieee754sp);
1681 union ieee754sp(*u) (union ieee754sp);
1682 } handler;
1683 union ieee754sp fd, fs, ft;
1684
1685 switch (MIPSInst_FUNC(ir)) {
1686 /* binary ops */
1687 case fadd_op:
1688 MIPS_FPU_EMU_INC_STATS(add_s);
1686 handler.b = ieee754sp_add;
1687 goto scopbop;
1688 case fsub_op:
1689 handler.b = ieee754sp_add;
1690 goto scopbop;
1691 case fsub_op:
1692 MIPS_FPU_EMU_INC_STATS(sub_s);
1689 handler.b = ieee754sp_sub;
1690 goto scopbop;
1691 case fmul_op:
1693 handler.b = ieee754sp_sub;
1694 goto scopbop;
1695 case fmul_op:
1696 MIPS_FPU_EMU_INC_STATS(mul_s);
1692 handler.b = ieee754sp_mul;
1693 goto scopbop;
1694 case fdiv_op:
1697 handler.b = ieee754sp_mul;
1698 goto scopbop;
1699 case fdiv_op:
1700 MIPS_FPU_EMU_INC_STATS(div_s);
1695 handler.b = ieee754sp_div;
1696 goto scopbop;
1697
1698 /* unary ops */
1699 case fsqrt_op:
1700 if (!cpu_has_mips_2_3_4_5_r)
1701 return SIGILL;
1702
1701 handler.b = ieee754sp_div;
1702 goto scopbop;
1703
1704 /* unary ops */
1705 case fsqrt_op:
1706 if (!cpu_has_mips_2_3_4_5_r)
1707 return SIGILL;
1708
1709 MIPS_FPU_EMU_INC_STATS(sqrt_s);
1703 handler.u = ieee754sp_sqrt;
1704 goto scopuop;
1705
1706 /*
1707 * Note that on some MIPS IV implementations such as the
1708 * R5000 and R8000 the FSQRT and FRECIP instructions do not
1709 * achieve full IEEE-754 accuracy - however this emulator does.
1710 */
1711 case frsqrt_op:
1712 if (!cpu_has_mips_4_5_64_r2_r6)
1713 return SIGILL;
1714
1710 handler.u = ieee754sp_sqrt;
1711 goto scopuop;
1712
1713 /*
1714 * Note that on some MIPS IV implementations such as the
1715 * R5000 and R8000 the FSQRT and FRECIP instructions do not
1716 * achieve full IEEE-754 accuracy - however this emulator does.
1717 */
1718 case frsqrt_op:
1719 if (!cpu_has_mips_4_5_64_r2_r6)
1720 return SIGILL;
1721
1722 MIPS_FPU_EMU_INC_STATS(rsqrt_s);
1715 handler.u = fpemu_sp_rsqrt;
1716 goto scopuop;
1717
1718 case frecip_op:
1719 if (!cpu_has_mips_4_5_64_r2_r6)
1720 return SIGILL;
1721
1723 handler.u = fpemu_sp_rsqrt;
1724 goto scopuop;
1725
1726 case frecip_op:
1727 if (!cpu_has_mips_4_5_64_r2_r6)
1728 return SIGILL;
1729
1730 MIPS_FPU_EMU_INC_STATS(recip_s);
1722 handler.u = fpemu_sp_recip;
1723 goto scopuop;
1724
1725 case fmovc_op:
1726 if (!cpu_has_mips_4_5_r)
1727 return SIGILL;
1728
1729 cond = fpucondbit[MIPSInst_FT(ir) >> 2];

--- 20 unchanged lines hidden (view full) ---

1750 return 0;
1751 SPFROMREG(rv.s, MIPSInst_FS(ir));
1752 break;
1753
1754 case fseleqz_op:
1755 if (!cpu_has_mips_r6)
1756 return SIGILL;
1757
1731 handler.u = fpemu_sp_recip;
1732 goto scopuop;
1733
1734 case fmovc_op:
1735 if (!cpu_has_mips_4_5_r)
1736 return SIGILL;
1737
1738 cond = fpucondbit[MIPSInst_FT(ir) >> 2];

--- 20 unchanged lines hidden (view full) ---

1759 return 0;
1760 SPFROMREG(rv.s, MIPSInst_FS(ir));
1761 break;
1762
1763 case fseleqz_op:
1764 if (!cpu_has_mips_r6)
1765 return SIGILL;
1766
1767 MIPS_FPU_EMU_INC_STATS(seleqz_s);
1758 SPFROMREG(rv.s, MIPSInst_FT(ir));
1759 if (rv.w & 0x1)
1760 rv.w = 0;
1761 else
1762 SPFROMREG(rv.s, MIPSInst_FS(ir));
1763 break;
1764
1765 case fselnez_op:
1766 if (!cpu_has_mips_r6)
1767 return SIGILL;
1768
1768 SPFROMREG(rv.s, MIPSInst_FT(ir));
1769 if (rv.w & 0x1)
1770 rv.w = 0;
1771 else
1772 SPFROMREG(rv.s, MIPSInst_FS(ir));
1773 break;
1774
1775 case fselnez_op:
1776 if (!cpu_has_mips_r6)
1777 return SIGILL;
1778
1779 MIPS_FPU_EMU_INC_STATS(selnez_s);
1769 SPFROMREG(rv.s, MIPSInst_FT(ir));
1770 if (rv.w & 0x1)
1771 SPFROMREG(rv.s, MIPSInst_FS(ir));
1772 else
1773 rv.w = 0;
1774 break;
1775
1776 case fmaddf_op: {
1777 union ieee754sp ft, fs, fd;
1778
1779 if (!cpu_has_mips_r6)
1780 return SIGILL;
1781
1780 SPFROMREG(rv.s, MIPSInst_FT(ir));
1781 if (rv.w & 0x1)
1782 SPFROMREG(rv.s, MIPSInst_FS(ir));
1783 else
1784 rv.w = 0;
1785 break;
1786
1787 case fmaddf_op: {
1788 union ieee754sp ft, fs, fd;
1789
1790 if (!cpu_has_mips_r6)
1791 return SIGILL;
1792
1793 MIPS_FPU_EMU_INC_STATS(maddf_s);
1782 SPFROMREG(ft, MIPSInst_FT(ir));
1783 SPFROMREG(fs, MIPSInst_FS(ir));
1784 SPFROMREG(fd, MIPSInst_FD(ir));
1785 rv.s = ieee754sp_maddf(fd, fs, ft);
1786 break;
1787 }
1788
1789 case fmsubf_op: {
1790 union ieee754sp ft, fs, fd;
1791
1792 if (!cpu_has_mips_r6)
1793 return SIGILL;
1794
1794 SPFROMREG(ft, MIPSInst_FT(ir));
1795 SPFROMREG(fs, MIPSInst_FS(ir));
1796 SPFROMREG(fd, MIPSInst_FD(ir));
1797 rv.s = ieee754sp_maddf(fd, fs, ft);
1798 break;
1799 }
1800
1801 case fmsubf_op: {
1802 union ieee754sp ft, fs, fd;
1803
1804 if (!cpu_has_mips_r6)
1805 return SIGILL;
1806
1807 MIPS_FPU_EMU_INC_STATS(msubf_s);
1795 SPFROMREG(ft, MIPSInst_FT(ir));
1796 SPFROMREG(fs, MIPSInst_FS(ir));
1797 SPFROMREG(fd, MIPSInst_FD(ir));
1798 rv.s = ieee754sp_msubf(fd, fs, ft);
1799 break;
1800 }
1801
1802 case frint_op: {
1803 union ieee754sp fs;
1804
1805 if (!cpu_has_mips_r6)
1806 return SIGILL;
1807
1808 SPFROMREG(ft, MIPSInst_FT(ir));
1809 SPFROMREG(fs, MIPSInst_FS(ir));
1810 SPFROMREG(fd, MIPSInst_FD(ir));
1811 rv.s = ieee754sp_msubf(fd, fs, ft);
1812 break;
1813 }
1814
1815 case frint_op: {
1816 union ieee754sp fs;
1817
1818 if (!cpu_has_mips_r6)
1819 return SIGILL;
1820
1821 MIPS_FPU_EMU_INC_STATS(rint_s);
1808 SPFROMREG(fs, MIPSInst_FS(ir));
1809 rv.s = ieee754sp_rint(fs);
1810 goto copcsr;
1811 }
1812
1813 case fclass_op: {
1814 union ieee754sp fs;
1815
1816 if (!cpu_has_mips_r6)
1817 return SIGILL;
1818
1822 SPFROMREG(fs, MIPSInst_FS(ir));
1823 rv.s = ieee754sp_rint(fs);
1824 goto copcsr;
1825 }
1826
1827 case fclass_op: {
1828 union ieee754sp fs;
1829
1830 if (!cpu_has_mips_r6)
1831 return SIGILL;
1832
1833 MIPS_FPU_EMU_INC_STATS(class_s);
1819 SPFROMREG(fs, MIPSInst_FS(ir));
1820 rv.w = ieee754sp_2008class(fs);
1821 rfmt = w_fmt;
1822 break;
1823 }
1824
1825 case fmin_op: {
1826 union ieee754sp fs, ft;
1827
1828 if (!cpu_has_mips_r6)
1829 return SIGILL;
1830
1834 SPFROMREG(fs, MIPSInst_FS(ir));
1835 rv.w = ieee754sp_2008class(fs);
1836 rfmt = w_fmt;
1837 break;
1838 }
1839
1840 case fmin_op: {
1841 union ieee754sp fs, ft;
1842
1843 if (!cpu_has_mips_r6)
1844 return SIGILL;
1845
1846 MIPS_FPU_EMU_INC_STATS(min_s);
1831 SPFROMREG(ft, MIPSInst_FT(ir));
1832 SPFROMREG(fs, MIPSInst_FS(ir));
1833 rv.s = ieee754sp_fmin(fs, ft);
1834 break;
1835 }
1836
1837 case fmina_op: {
1838 union ieee754sp fs, ft;
1839
1840 if (!cpu_has_mips_r6)
1841 return SIGILL;
1842
1847 SPFROMREG(ft, MIPSInst_FT(ir));
1848 SPFROMREG(fs, MIPSInst_FS(ir));
1849 rv.s = ieee754sp_fmin(fs, ft);
1850 break;
1851 }
1852
1853 case fmina_op: {
1854 union ieee754sp fs, ft;
1855
1856 if (!cpu_has_mips_r6)
1857 return SIGILL;
1858
1859 MIPS_FPU_EMU_INC_STATS(mina_s);
1843 SPFROMREG(ft, MIPSInst_FT(ir));
1844 SPFROMREG(fs, MIPSInst_FS(ir));
1845 rv.s = ieee754sp_fmina(fs, ft);
1846 break;
1847 }
1848
1849 case fmax_op: {
1850 union ieee754sp fs, ft;
1851
1852 if (!cpu_has_mips_r6)
1853 return SIGILL;
1854
1860 SPFROMREG(ft, MIPSInst_FT(ir));
1861 SPFROMREG(fs, MIPSInst_FS(ir));
1862 rv.s = ieee754sp_fmina(fs, ft);
1863 break;
1864 }
1865
1866 case fmax_op: {
1867 union ieee754sp fs, ft;
1868
1869 if (!cpu_has_mips_r6)
1870 return SIGILL;
1871
1872 MIPS_FPU_EMU_INC_STATS(max_s);
1855 SPFROMREG(ft, MIPSInst_FT(ir));
1856 SPFROMREG(fs, MIPSInst_FS(ir));
1857 rv.s = ieee754sp_fmax(fs, ft);
1858 break;
1859 }
1860
1861 case fmaxa_op: {
1862 union ieee754sp fs, ft;
1863
1864 if (!cpu_has_mips_r6)
1865 return SIGILL;
1866
1873 SPFROMREG(ft, MIPSInst_FT(ir));
1874 SPFROMREG(fs, MIPSInst_FS(ir));
1875 rv.s = ieee754sp_fmax(fs, ft);
1876 break;
1877 }
1878
1879 case fmaxa_op: {
1880 union ieee754sp fs, ft;
1881
1882 if (!cpu_has_mips_r6)
1883 return SIGILL;
1884
1885 MIPS_FPU_EMU_INC_STATS(maxa_s);
1867 SPFROMREG(ft, MIPSInst_FT(ir));
1868 SPFROMREG(fs, MIPSInst_FS(ir));
1869 rv.s = ieee754sp_fmaxa(fs, ft);
1870 break;
1871 }
1872
1873 case fabs_op:
1886 SPFROMREG(ft, MIPSInst_FT(ir));
1887 SPFROMREG(fs, MIPSInst_FS(ir));
1888 rv.s = ieee754sp_fmaxa(fs, ft);
1889 break;
1890 }
1891
1892 case fabs_op:
1893 MIPS_FPU_EMU_INC_STATS(abs_s);
1874 handler.u = ieee754sp_abs;
1875 goto scopuop;
1876
1877 case fneg_op:
1894 handler.u = ieee754sp_abs;
1895 goto scopuop;
1896
1897 case fneg_op:
1898 MIPS_FPU_EMU_INC_STATS(neg_s);
1878 handler.u = ieee754sp_neg;
1879 goto scopuop;
1880
1881 case fmov_op:
1882 /* an easy one */
1899 handler.u = ieee754sp_neg;
1900 goto scopuop;
1901
1902 case fmov_op:
1903 /* an easy one */
1904 MIPS_FPU_EMU_INC_STATS(mov_s);
1883 SPFROMREG(rv.s, MIPSInst_FS(ir));
1884 goto copcsr;
1885
1886 /* binary op on handler */
1887scopbop:
1888 SPFROMREG(fs, MIPSInst_FS(ir));
1889 SPFROMREG(ft, MIPSInst_FT(ir));
1890

--- 26 unchanged lines hidden (view full) ---

1917 }
1918 break;
1919
1920 /* unary conv ops */
1921 case fcvts_op:
1922 return SIGILL; /* not defined */
1923
1924 case fcvtd_op:
1905 SPFROMREG(rv.s, MIPSInst_FS(ir));
1906 goto copcsr;
1907
1908 /* binary op on handler */
1909scopbop:
1910 SPFROMREG(fs, MIPSInst_FS(ir));
1911 SPFROMREG(ft, MIPSInst_FT(ir));
1912

--- 26 unchanged lines hidden (view full) ---

1939 }
1940 break;
1941
1942 /* unary conv ops */
1943 case fcvts_op:
1944 return SIGILL; /* not defined */
1945
1946 case fcvtd_op:
1947 MIPS_FPU_EMU_INC_STATS(cvt_d_s);
1925 SPFROMREG(fs, MIPSInst_FS(ir));
1926 rv.d = ieee754dp_fsp(fs);
1927 rfmt = d_fmt;
1928 goto copcsr;
1929
1930 case fcvtw_op:
1948 SPFROMREG(fs, MIPSInst_FS(ir));
1949 rv.d = ieee754dp_fsp(fs);
1950 rfmt = d_fmt;
1951 goto copcsr;
1952
1953 case fcvtw_op:
1954 MIPS_FPU_EMU_INC_STATS(cvt_w_s);
1931 SPFROMREG(fs, MIPSInst_FS(ir));
1932 rv.w = ieee754sp_tint(fs);
1933 rfmt = w_fmt;
1934 goto copcsr;
1935
1936 case fround_op:
1937 case ftrunc_op:
1938 case fceil_op:
1939 case ffloor_op:
1940 if (!cpu_has_mips_2_3_4_5_r)
1941 return SIGILL;
1942
1955 SPFROMREG(fs, MIPSInst_FS(ir));
1956 rv.w = ieee754sp_tint(fs);
1957 rfmt = w_fmt;
1958 goto copcsr;
1959
1960 case fround_op:
1961 case ftrunc_op:
1962 case fceil_op:
1963 case ffloor_op:
1964 if (!cpu_has_mips_2_3_4_5_r)
1965 return SIGILL;
1966
1967 if (MIPSInst_FUNC(ir) == fceil_op)
1968 MIPS_FPU_EMU_INC_STATS(ceil_w_s);
1969 if (MIPSInst_FUNC(ir) == ffloor_op)
1970 MIPS_FPU_EMU_INC_STATS(floor_w_s);
1971 if (MIPSInst_FUNC(ir) == fround_op)
1972 MIPS_FPU_EMU_INC_STATS(round_w_s);
1973 if (MIPSInst_FUNC(ir) == ftrunc_op)
1974 MIPS_FPU_EMU_INC_STATS(trunc_w_s);
1975
1943 oldrm = ieee754_csr.rm;
1944 SPFROMREG(fs, MIPSInst_FS(ir));
1945 ieee754_csr.rm = MIPSInst_FUNC(ir);
1946 rv.w = ieee754sp_tint(fs);
1947 ieee754_csr.rm = oldrm;
1948 rfmt = w_fmt;
1949 goto copcsr;
1950
1951 case fsel_op:
1952 if (!cpu_has_mips_r6)
1953 return SIGILL;
1954
1976 oldrm = ieee754_csr.rm;
1977 SPFROMREG(fs, MIPSInst_FS(ir));
1978 ieee754_csr.rm = MIPSInst_FUNC(ir);
1979 rv.w = ieee754sp_tint(fs);
1980 ieee754_csr.rm = oldrm;
1981 rfmt = w_fmt;
1982 goto copcsr;
1983
1984 case fsel_op:
1985 if (!cpu_has_mips_r6)
1986 return SIGILL;
1987
1988 MIPS_FPU_EMU_INC_STATS(sel_s);
1955 SPFROMREG(fd, MIPSInst_FD(ir));
1956 if (fd.bits & 0x1)
1957 SPFROMREG(rv.s, MIPSInst_FT(ir));
1958 else
1959 SPFROMREG(rv.s, MIPSInst_FS(ir));
1960 break;
1961
1962 case fcvtl_op:
1963 if (!cpu_has_mips_3_4_5_64_r2_r6)
1964 return SIGILL;
1965
1989 SPFROMREG(fd, MIPSInst_FD(ir));
1990 if (fd.bits & 0x1)
1991 SPFROMREG(rv.s, MIPSInst_FT(ir));
1992 else
1993 SPFROMREG(rv.s, MIPSInst_FS(ir));
1994 break;
1995
1996 case fcvtl_op:
1997 if (!cpu_has_mips_3_4_5_64_r2_r6)
1998 return SIGILL;
1999
2000 MIPS_FPU_EMU_INC_STATS(cvt_l_s);
1966 SPFROMREG(fs, MIPSInst_FS(ir));
1967 rv.l = ieee754sp_tlong(fs);
1968 rfmt = l_fmt;
1969 goto copcsr;
1970
1971 case froundl_op:
1972 case ftruncl_op:
1973 case fceill_op:
1974 case ffloorl_op:
1975 if (!cpu_has_mips_3_4_5_64_r2_r6)
1976 return SIGILL;
1977
2001 SPFROMREG(fs, MIPSInst_FS(ir));
2002 rv.l = ieee754sp_tlong(fs);
2003 rfmt = l_fmt;
2004 goto copcsr;
2005
2006 case froundl_op:
2007 case ftruncl_op:
2008 case fceill_op:
2009 case ffloorl_op:
2010 if (!cpu_has_mips_3_4_5_64_r2_r6)
2011 return SIGILL;
2012
2013 if (MIPSInst_FUNC(ir) == fceill_op)
2014 MIPS_FPU_EMU_INC_STATS(ceil_l_s);
2015 if (MIPSInst_FUNC(ir) == ffloorl_op)
2016 MIPS_FPU_EMU_INC_STATS(floor_l_s);
2017 if (MIPSInst_FUNC(ir) == froundl_op)
2018 MIPS_FPU_EMU_INC_STATS(round_l_s);
2019 if (MIPSInst_FUNC(ir) == ftruncl_op)
2020 MIPS_FPU_EMU_INC_STATS(trunc_l_s);
2021
1978 oldrm = ieee754_csr.rm;
1979 SPFROMREG(fs, MIPSInst_FS(ir));
1980 ieee754_csr.rm = MIPSInst_FUNC(ir);
1981 rv.l = ieee754sp_tlong(fs);
1982 ieee754_csr.rm = oldrm;
1983 rfmt = l_fmt;
1984 goto copcsr;
1985

--- 25 unchanged lines hidden (view full) ---

2011 union {
2012 union ieee754dp(*b) (union ieee754dp, union ieee754dp);
2013 union ieee754dp(*u) (union ieee754dp);
2014 } handler;
2015
2016 switch (MIPSInst_FUNC(ir)) {
2017 /* binary ops */
2018 case fadd_op:
2022 oldrm = ieee754_csr.rm;
2023 SPFROMREG(fs, MIPSInst_FS(ir));
2024 ieee754_csr.rm = MIPSInst_FUNC(ir);
2025 rv.l = ieee754sp_tlong(fs);
2026 ieee754_csr.rm = oldrm;
2027 rfmt = l_fmt;
2028 goto copcsr;
2029

--- 25 unchanged lines hidden (view full) ---

2055 union {
2056 union ieee754dp(*b) (union ieee754dp, union ieee754dp);
2057 union ieee754dp(*u) (union ieee754dp);
2058 } handler;
2059
2060 switch (MIPSInst_FUNC(ir)) {
2061 /* binary ops */
2062 case fadd_op:
2063 MIPS_FPU_EMU_INC_STATS(add_d);
2019 handler.b = ieee754dp_add;
2020 goto dcopbop;
2021 case fsub_op:
2064 handler.b = ieee754dp_add;
2065 goto dcopbop;
2066 case fsub_op:
2067 MIPS_FPU_EMU_INC_STATS(sub_d);
2022 handler.b = ieee754dp_sub;
2023 goto dcopbop;
2024 case fmul_op:
2068 handler.b = ieee754dp_sub;
2069 goto dcopbop;
2070 case fmul_op:
2071 MIPS_FPU_EMU_INC_STATS(mul_d);
2025 handler.b = ieee754dp_mul;
2026 goto dcopbop;
2027 case fdiv_op:
2072 handler.b = ieee754dp_mul;
2073 goto dcopbop;
2074 case fdiv_op:
2075 MIPS_FPU_EMU_INC_STATS(div_d);
2028 handler.b = ieee754dp_div;
2029 goto dcopbop;
2030
2031 /* unary ops */
2032 case fsqrt_op:
2033 if (!cpu_has_mips_2_3_4_5_r)
2034 return SIGILL;
2035
2076 handler.b = ieee754dp_div;
2077 goto dcopbop;
2078
2079 /* unary ops */
2080 case fsqrt_op:
2081 if (!cpu_has_mips_2_3_4_5_r)
2082 return SIGILL;
2083
2084 MIPS_FPU_EMU_INC_STATS(sqrt_d);
2036 handler.u = ieee754dp_sqrt;
2037 goto dcopuop;
2038 /*
2039 * Note that on some MIPS IV implementations such as the
2040 * R5000 and R8000 the FSQRT and FRECIP instructions do not
2041 * achieve full IEEE-754 accuracy - however this emulator does.
2042 */
2043 case frsqrt_op:
2044 if (!cpu_has_mips_4_5_64_r2_r6)
2045 return SIGILL;
2046
2085 handler.u = ieee754dp_sqrt;
2086 goto dcopuop;
2087 /*
2088 * Note that on some MIPS IV implementations such as the
2089 * R5000 and R8000 the FSQRT and FRECIP instructions do not
2090 * achieve full IEEE-754 accuracy - however this emulator does.
2091 */
2092 case frsqrt_op:
2093 if (!cpu_has_mips_4_5_64_r2_r6)
2094 return SIGILL;
2095
2096 MIPS_FPU_EMU_INC_STATS(rsqrt_d);
2047 handler.u = fpemu_dp_rsqrt;
2048 goto dcopuop;
2049 case frecip_op:
2050 if (!cpu_has_mips_4_5_64_r2_r6)
2051 return SIGILL;
2052
2097 handler.u = fpemu_dp_rsqrt;
2098 goto dcopuop;
2099 case frecip_op:
2100 if (!cpu_has_mips_4_5_64_r2_r6)
2101 return SIGILL;
2102
2103 MIPS_FPU_EMU_INC_STATS(recip_d);
2053 handler.u = fpemu_dp_recip;
2054 goto dcopuop;
2055 case fmovc_op:
2056 if (!cpu_has_mips_4_5_r)
2057 return SIGILL;
2058
2059 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
2060 if (((ctx->fcr31 & cond) != 0) !=

--- 17 unchanged lines hidden (view full) ---

2078 return 0;
2079 DPFROMREG(rv.d, MIPSInst_FS(ir));
2080 break;
2081
2082 case fseleqz_op:
2083 if (!cpu_has_mips_r6)
2084 return SIGILL;
2085
2104 handler.u = fpemu_dp_recip;
2105 goto dcopuop;
2106 case fmovc_op:
2107 if (!cpu_has_mips_4_5_r)
2108 return SIGILL;
2109
2110 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
2111 if (((ctx->fcr31 & cond) != 0) !=

--- 17 unchanged lines hidden (view full) ---

2129 return 0;
2130 DPFROMREG(rv.d, MIPSInst_FS(ir));
2131 break;
2132
2133 case fseleqz_op:
2134 if (!cpu_has_mips_r6)
2135 return SIGILL;
2136
2137 MIPS_FPU_EMU_INC_STATS(seleqz_d);
2086 DPFROMREG(rv.d, MIPSInst_FT(ir));
2087 if (rv.l & 0x1)
2088 rv.l = 0;
2089 else
2090 DPFROMREG(rv.d, MIPSInst_FS(ir));
2091 break;
2092
2093 case fselnez_op:
2094 if (!cpu_has_mips_r6)
2095 return SIGILL;
2096
2138 DPFROMREG(rv.d, MIPSInst_FT(ir));
2139 if (rv.l & 0x1)
2140 rv.l = 0;
2141 else
2142 DPFROMREG(rv.d, MIPSInst_FS(ir));
2143 break;
2144
2145 case fselnez_op:
2146 if (!cpu_has_mips_r6)
2147 return SIGILL;
2148
2149 MIPS_FPU_EMU_INC_STATS(selnez_d);
2097 DPFROMREG(rv.d, MIPSInst_FT(ir));
2098 if (rv.l & 0x1)
2099 DPFROMREG(rv.d, MIPSInst_FS(ir));
2100 else
2101 rv.l = 0;
2102 break;
2103
2104 case fmaddf_op: {
2105 union ieee754dp ft, fs, fd;
2106
2107 if (!cpu_has_mips_r6)
2108 return SIGILL;
2109
2150 DPFROMREG(rv.d, MIPSInst_FT(ir));
2151 if (rv.l & 0x1)
2152 DPFROMREG(rv.d, MIPSInst_FS(ir));
2153 else
2154 rv.l = 0;
2155 break;
2156
2157 case fmaddf_op: {
2158 union ieee754dp ft, fs, fd;
2159
2160 if (!cpu_has_mips_r6)
2161 return SIGILL;
2162
2163 MIPS_FPU_EMU_INC_STATS(maddf_d);
2110 DPFROMREG(ft, MIPSInst_FT(ir));
2111 DPFROMREG(fs, MIPSInst_FS(ir));
2112 DPFROMREG(fd, MIPSInst_FD(ir));
2113 rv.d = ieee754dp_maddf(fd, fs, ft);
2114 break;
2115 }
2116
2117 case fmsubf_op: {
2118 union ieee754dp ft, fs, fd;
2119
2120 if (!cpu_has_mips_r6)
2121 return SIGILL;
2122
2164 DPFROMREG(ft, MIPSInst_FT(ir));
2165 DPFROMREG(fs, MIPSInst_FS(ir));
2166 DPFROMREG(fd, MIPSInst_FD(ir));
2167 rv.d = ieee754dp_maddf(fd, fs, ft);
2168 break;
2169 }
2170
2171 case fmsubf_op: {
2172 union ieee754dp ft, fs, fd;
2173
2174 if (!cpu_has_mips_r6)
2175 return SIGILL;
2176
2177 MIPS_FPU_EMU_INC_STATS(msubf_d);
2123 DPFROMREG(ft, MIPSInst_FT(ir));
2124 DPFROMREG(fs, MIPSInst_FS(ir));
2125 DPFROMREG(fd, MIPSInst_FD(ir));
2126 rv.d = ieee754dp_msubf(fd, fs, ft);
2127 break;
2128 }
2129
2130 case frint_op: {
2131 union ieee754dp fs;
2132
2133 if (!cpu_has_mips_r6)
2134 return SIGILL;
2135
2178 DPFROMREG(ft, MIPSInst_FT(ir));
2179 DPFROMREG(fs, MIPSInst_FS(ir));
2180 DPFROMREG(fd, MIPSInst_FD(ir));
2181 rv.d = ieee754dp_msubf(fd, fs, ft);
2182 break;
2183 }
2184
2185 case frint_op: {
2186 union ieee754dp fs;
2187
2188 if (!cpu_has_mips_r6)
2189 return SIGILL;
2190
2191 MIPS_FPU_EMU_INC_STATS(rint_d);
2136 DPFROMREG(fs, MIPSInst_FS(ir));
2137 rv.d = ieee754dp_rint(fs);
2138 goto copcsr;
2139 }
2140
2141 case fclass_op: {
2142 union ieee754dp fs;
2143
2144 if (!cpu_has_mips_r6)
2145 return SIGILL;
2146
2192 DPFROMREG(fs, MIPSInst_FS(ir));
2193 rv.d = ieee754dp_rint(fs);
2194 goto copcsr;
2195 }
2196
2197 case fclass_op: {
2198 union ieee754dp fs;
2199
2200 if (!cpu_has_mips_r6)
2201 return SIGILL;
2202
2203 MIPS_FPU_EMU_INC_STATS(class_d);
2147 DPFROMREG(fs, MIPSInst_FS(ir));
2148 rv.l = ieee754dp_2008class(fs);
2149 rfmt = l_fmt;
2150 break;
2151 }
2152
2153 case fmin_op: {
2154 union ieee754dp fs, ft;
2155
2156 if (!cpu_has_mips_r6)
2157 return SIGILL;
2158
2204 DPFROMREG(fs, MIPSInst_FS(ir));
2205 rv.l = ieee754dp_2008class(fs);
2206 rfmt = l_fmt;
2207 break;
2208 }
2209
2210 case fmin_op: {
2211 union ieee754dp fs, ft;
2212
2213 if (!cpu_has_mips_r6)
2214 return SIGILL;
2215
2216 MIPS_FPU_EMU_INC_STATS(min_d);
2159 DPFROMREG(ft, MIPSInst_FT(ir));
2160 DPFROMREG(fs, MIPSInst_FS(ir));
2161 rv.d = ieee754dp_fmin(fs, ft);
2162 break;
2163 }
2164
2165 case fmina_op: {
2166 union ieee754dp fs, ft;
2167
2168 if (!cpu_has_mips_r6)
2169 return SIGILL;
2170
2217 DPFROMREG(ft, MIPSInst_FT(ir));
2218 DPFROMREG(fs, MIPSInst_FS(ir));
2219 rv.d = ieee754dp_fmin(fs, ft);
2220 break;
2221 }
2222
2223 case fmina_op: {
2224 union ieee754dp fs, ft;
2225
2226 if (!cpu_has_mips_r6)
2227 return SIGILL;
2228
2229 MIPS_FPU_EMU_INC_STATS(mina_d);
2171 DPFROMREG(ft, MIPSInst_FT(ir));
2172 DPFROMREG(fs, MIPSInst_FS(ir));
2173 rv.d = ieee754dp_fmina(fs, ft);
2174 break;
2175 }
2176
2177 case fmax_op: {
2178 union ieee754dp fs, ft;
2179
2180 if (!cpu_has_mips_r6)
2181 return SIGILL;
2182
2230 DPFROMREG(ft, MIPSInst_FT(ir));
2231 DPFROMREG(fs, MIPSInst_FS(ir));
2232 rv.d = ieee754dp_fmina(fs, ft);
2233 break;
2234 }
2235
2236 case fmax_op: {
2237 union ieee754dp fs, ft;
2238
2239 if (!cpu_has_mips_r6)
2240 return SIGILL;
2241
2242 MIPS_FPU_EMU_INC_STATS(max_d);
2183 DPFROMREG(ft, MIPSInst_FT(ir));
2184 DPFROMREG(fs, MIPSInst_FS(ir));
2185 rv.d = ieee754dp_fmax(fs, ft);
2186 break;
2187 }
2188
2189 case fmaxa_op: {
2190 union ieee754dp fs, ft;
2191
2192 if (!cpu_has_mips_r6)
2193 return SIGILL;
2194
2243 DPFROMREG(ft, MIPSInst_FT(ir));
2244 DPFROMREG(fs, MIPSInst_FS(ir));
2245 rv.d = ieee754dp_fmax(fs, ft);
2246 break;
2247 }
2248
2249 case fmaxa_op: {
2250 union ieee754dp fs, ft;
2251
2252 if (!cpu_has_mips_r6)
2253 return SIGILL;
2254
2255 MIPS_FPU_EMU_INC_STATS(maxa_d);
2195 DPFROMREG(ft, MIPSInst_FT(ir));
2196 DPFROMREG(fs, MIPSInst_FS(ir));
2197 rv.d = ieee754dp_fmaxa(fs, ft);
2198 break;
2199 }
2200
2201 case fabs_op:
2256 DPFROMREG(ft, MIPSInst_FT(ir));
2257 DPFROMREG(fs, MIPSInst_FS(ir));
2258 rv.d = ieee754dp_fmaxa(fs, ft);
2259 break;
2260 }
2261
2262 case fabs_op:
2263 MIPS_FPU_EMU_INC_STATS(abs_d);
2202 handler.u = ieee754dp_abs;
2203 goto dcopuop;
2204
2205 case fneg_op:
2264 handler.u = ieee754dp_abs;
2265 goto dcopuop;
2266
2267 case fneg_op:
2268 MIPS_FPU_EMU_INC_STATS(neg_d);
2206 handler.u = ieee754dp_neg;
2207 goto dcopuop;
2208
2209 case fmov_op:
2210 /* an easy one */
2269 handler.u = ieee754dp_neg;
2270 goto dcopuop;
2271
2272 case fmov_op:
2273 /* an easy one */
2274 MIPS_FPU_EMU_INC_STATS(mov_d);
2211 DPFROMREG(rv.d, MIPSInst_FS(ir));
2212 goto copcsr;
2213
2214 /* binary op on handler */
2215dcopbop:
2216 DPFROMREG(fs, MIPSInst_FS(ir));
2217 DPFROMREG(ft, MIPSInst_FT(ir));
2218
2219 rv.d = (*handler.b) (fs, ft);
2220 goto copcsr;
2221dcopuop:
2222 DPFROMREG(fs, MIPSInst_FS(ir));
2223 rv.d = (*handler.u) (fs);
2224 goto copcsr;
2225
2226 /*
2227 * unary conv ops
2228 */
2229 case fcvts_op:
2275 DPFROMREG(rv.d, MIPSInst_FS(ir));
2276 goto copcsr;
2277
2278 /* binary op on handler */
2279dcopbop:
2280 DPFROMREG(fs, MIPSInst_FS(ir));
2281 DPFROMREG(ft, MIPSInst_FT(ir));
2282
2283 rv.d = (*handler.b) (fs, ft);
2284 goto copcsr;
2285dcopuop:
2286 DPFROMREG(fs, MIPSInst_FS(ir));
2287 rv.d = (*handler.u) (fs);
2288 goto copcsr;
2289
2290 /*
2291 * unary conv ops
2292 */
2293 case fcvts_op:
2294 MIPS_FPU_EMU_INC_STATS(cvt_s_d);
2230 DPFROMREG(fs, MIPSInst_FS(ir));
2231 rv.s = ieee754sp_fdp(fs);
2232 rfmt = s_fmt;
2233 goto copcsr;
2234
2235 case fcvtd_op:
2236 return SIGILL; /* not defined */
2237
2238 case fcvtw_op:
2295 DPFROMREG(fs, MIPSInst_FS(ir));
2296 rv.s = ieee754sp_fdp(fs);
2297 rfmt = s_fmt;
2298 goto copcsr;
2299
2300 case fcvtd_op:
2301 return SIGILL; /* not defined */
2302
2303 case fcvtw_op:
2304 MIPS_FPU_EMU_INC_STATS(cvt_w_d);
2239 DPFROMREG(fs, MIPSInst_FS(ir));
2240 rv.w = ieee754dp_tint(fs); /* wrong */
2241 rfmt = w_fmt;
2242 goto copcsr;
2243
2244 case fround_op:
2245 case ftrunc_op:
2246 case fceil_op:
2247 case ffloor_op:
2248 if (!cpu_has_mips_2_3_4_5_r)
2249 return SIGILL;
2250
2305 DPFROMREG(fs, MIPSInst_FS(ir));
2306 rv.w = ieee754dp_tint(fs); /* wrong */
2307 rfmt = w_fmt;
2308 goto copcsr;
2309
2310 case fround_op:
2311 case ftrunc_op:
2312 case fceil_op:
2313 case ffloor_op:
2314 if (!cpu_has_mips_2_3_4_5_r)
2315 return SIGILL;
2316
2317 if (MIPSInst_FUNC(ir) == fceil_op)
2318 MIPS_FPU_EMU_INC_STATS(ceil_w_d);
2319 if (MIPSInst_FUNC(ir) == ffloor_op)
2320 MIPS_FPU_EMU_INC_STATS(floor_w_d);
2321 if (MIPSInst_FUNC(ir) == fround_op)
2322 MIPS_FPU_EMU_INC_STATS(round_w_d);
2323 if (MIPSInst_FUNC(ir) == ftrunc_op)
2324 MIPS_FPU_EMU_INC_STATS(trunc_w_d);
2325
2251 oldrm = ieee754_csr.rm;
2252 DPFROMREG(fs, MIPSInst_FS(ir));
2253 ieee754_csr.rm = MIPSInst_FUNC(ir);
2254 rv.w = ieee754dp_tint(fs);
2255 ieee754_csr.rm = oldrm;
2256 rfmt = w_fmt;
2257 goto copcsr;
2258
2259 case fsel_op:
2260 if (!cpu_has_mips_r6)
2261 return SIGILL;
2262
2326 oldrm = ieee754_csr.rm;
2327 DPFROMREG(fs, MIPSInst_FS(ir));
2328 ieee754_csr.rm = MIPSInst_FUNC(ir);
2329 rv.w = ieee754dp_tint(fs);
2330 ieee754_csr.rm = oldrm;
2331 rfmt = w_fmt;
2332 goto copcsr;
2333
2334 case fsel_op:
2335 if (!cpu_has_mips_r6)
2336 return SIGILL;
2337
2338 MIPS_FPU_EMU_INC_STATS(sel_d);
2263 DPFROMREG(fd, MIPSInst_FD(ir));
2264 if (fd.bits & 0x1)
2265 DPFROMREG(rv.d, MIPSInst_FT(ir));
2266 else
2267 DPFROMREG(rv.d, MIPSInst_FS(ir));
2268 break;
2269
2270 case fcvtl_op:
2271 if (!cpu_has_mips_3_4_5_64_r2_r6)
2272 return SIGILL;
2273
2339 DPFROMREG(fd, MIPSInst_FD(ir));
2340 if (fd.bits & 0x1)
2341 DPFROMREG(rv.d, MIPSInst_FT(ir));
2342 else
2343 DPFROMREG(rv.d, MIPSInst_FS(ir));
2344 break;
2345
2346 case fcvtl_op:
2347 if (!cpu_has_mips_3_4_5_64_r2_r6)
2348 return SIGILL;
2349
2350 MIPS_FPU_EMU_INC_STATS(cvt_l_d);
2274 DPFROMREG(fs, MIPSInst_FS(ir));
2275 rv.l = ieee754dp_tlong(fs);
2276 rfmt = l_fmt;
2277 goto copcsr;
2278
2279 case froundl_op:
2280 case ftruncl_op:
2281 case fceill_op:
2282 case ffloorl_op:
2283 if (!cpu_has_mips_3_4_5_64_r2_r6)
2284 return SIGILL;
2285
2351 DPFROMREG(fs, MIPSInst_FS(ir));
2352 rv.l = ieee754dp_tlong(fs);
2353 rfmt = l_fmt;
2354 goto copcsr;
2355
2356 case froundl_op:
2357 case ftruncl_op:
2358 case fceill_op:
2359 case ffloorl_op:
2360 if (!cpu_has_mips_3_4_5_64_r2_r6)
2361 return SIGILL;
2362
2363 if (MIPSInst_FUNC(ir) == fceill_op)
2364 MIPS_FPU_EMU_INC_STATS(ceil_l_d);
2365 if (MIPSInst_FUNC(ir) == ffloorl_op)
2366 MIPS_FPU_EMU_INC_STATS(floor_l_d);
2367 if (MIPSInst_FUNC(ir) == froundl_op)
2368 MIPS_FPU_EMU_INC_STATS(round_l_d);
2369 if (MIPSInst_FUNC(ir) == ftruncl_op)
2370 MIPS_FPU_EMU_INC_STATS(trunc_l_d);
2371
2286 oldrm = ieee754_csr.rm;
2287 DPFROMREG(fs, MIPSInst_FS(ir));
2288 ieee754_csr.rm = MIPSInst_FUNC(ir);
2289 rv.l = ieee754dp_tlong(fs);
2290 ieee754_csr.rm = oldrm;
2291 rfmt = l_fmt;
2292 goto copcsr;
2293

--- 25 unchanged lines hidden (view full) ---

2319 }
2320
2321 case w_fmt: {
2322 union ieee754dp fs;
2323
2324 switch (MIPSInst_FUNC(ir)) {
2325 case fcvts_op:
2326 /* convert word to single precision real */
2372 oldrm = ieee754_csr.rm;
2373 DPFROMREG(fs, MIPSInst_FS(ir));
2374 ieee754_csr.rm = MIPSInst_FUNC(ir);
2375 rv.l = ieee754dp_tlong(fs);
2376 ieee754_csr.rm = oldrm;
2377 rfmt = l_fmt;
2378 goto copcsr;
2379

--- 25 unchanged lines hidden (view full) ---

2405 }
2406
2407 case w_fmt: {
2408 union ieee754dp fs;
2409
2410 switch (MIPSInst_FUNC(ir)) {
2411 case fcvts_op:
2412 /* convert word to single precision real */
2413 MIPS_FPU_EMU_INC_STATS(cvt_s_w);
2327 SPFROMREG(fs, MIPSInst_FS(ir));
2328 rv.s = ieee754sp_fint(fs.bits);
2329 rfmt = s_fmt;
2330 goto copcsr;
2331 case fcvtd_op:
2332 /* convert word to double precision real */
2414 SPFROMREG(fs, MIPSInst_FS(ir));
2415 rv.s = ieee754sp_fint(fs.bits);
2416 rfmt = s_fmt;
2417 goto copcsr;
2418 case fcvtd_op:
2419 /* convert word to double precision real */
2420 MIPS_FPU_EMU_INC_STATS(cvt_d_w);
2333 SPFROMREG(fs, MIPSInst_FS(ir));
2334 rv.d = ieee754dp_fint(fs.bits);
2335 rfmt = d_fmt;
2336 goto copcsr;
2337 default: {
2338 /* Emulating the new CMP.condn.fmt R6 instruction */
2339#define CMPOP_MASK 0x7
2340#define SIGN_BIT (0x1 << 3)
2341#define PREDICATE_BIT (0x1 << 4)
2342
2343 int cmpop = MIPSInst_FUNC(ir) & CMPOP_MASK;
2344 int sig = MIPSInst_FUNC(ir) & SIGN_BIT;
2345 union ieee754sp fs, ft;
2346
2347 /* This is an R6 only instruction */
2348 if (!cpu_has_mips_r6 ||
2349 (MIPSInst_FUNC(ir) & 0x20))
2350 return SIGILL;
2351
2421 SPFROMREG(fs, MIPSInst_FS(ir));
2422 rv.d = ieee754dp_fint(fs.bits);
2423 rfmt = d_fmt;
2424 goto copcsr;
2425 default: {
2426 /* Emulating the new CMP.condn.fmt R6 instruction */
2427#define CMPOP_MASK 0x7
2428#define SIGN_BIT (0x1 << 3)
2429#define PREDICATE_BIT (0x1 << 4)
2430
2431 int cmpop = MIPSInst_FUNC(ir) & CMPOP_MASK;
2432 int sig = MIPSInst_FUNC(ir) & SIGN_BIT;
2433 union ieee754sp fs, ft;
2434
2435 /* This is an R6 only instruction */
2436 if (!cpu_has_mips_r6 ||
2437 (MIPSInst_FUNC(ir) & 0x20))
2438 return SIGILL;
2439
2440 if (!sig) {
2441 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {
2442 switch (cmpop) {
2443 case 0:
2444 MIPS_FPU_EMU_INC_STATS(cmp_af_s);
2445 break;
2446 case 1:
2447 MIPS_FPU_EMU_INC_STATS(cmp_un_s);
2448 break;
2449 case 2:
2450 MIPS_FPU_EMU_INC_STATS(cmp_eq_s);
2451 break;
2452 case 3:
2453 MIPS_FPU_EMU_INC_STATS(cmp_ueq_s);
2454 break;
2455 case 4:
2456 MIPS_FPU_EMU_INC_STATS(cmp_lt_s);
2457 break;
2458 case 5:
2459 MIPS_FPU_EMU_INC_STATS(cmp_ult_s);
2460 break;
2461 case 6:
2462 MIPS_FPU_EMU_INC_STATS(cmp_le_s);
2463 break;
2464 case 7:
2465 MIPS_FPU_EMU_INC_STATS(cmp_ule_s);
2466 break;
2467 }
2468 } else {
2469 switch (cmpop) {
2470 case 1:
2471 MIPS_FPU_EMU_INC_STATS(cmp_or_s);
2472 break;
2473 case 2:
2474 MIPS_FPU_EMU_INC_STATS(cmp_une_s);
2475 break;
2476 case 3:
2477 MIPS_FPU_EMU_INC_STATS(cmp_ne_s);
2478 break;
2479 }
2480 }
2481 } else {
2482 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {
2483 switch (cmpop) {
2484 case 0:
2485 MIPS_FPU_EMU_INC_STATS(cmp_saf_s);
2486 break;
2487 case 1:
2488 MIPS_FPU_EMU_INC_STATS(cmp_sun_s);
2489 break;
2490 case 2:
2491 MIPS_FPU_EMU_INC_STATS(cmp_seq_s);
2492 break;
2493 case 3:
2494 MIPS_FPU_EMU_INC_STATS(cmp_sueq_s);
2495 break;
2496 case 4:
2497 MIPS_FPU_EMU_INC_STATS(cmp_slt_s);
2498 break;
2499 case 5:
2500 MIPS_FPU_EMU_INC_STATS(cmp_sult_s);
2501 break;
2502 case 6:
2503 MIPS_FPU_EMU_INC_STATS(cmp_sle_s);
2504 break;
2505 case 7:
2506 MIPS_FPU_EMU_INC_STATS(cmp_sule_s);
2507 break;
2508 }
2509 } else {
2510 switch (cmpop) {
2511 case 1:
2512 MIPS_FPU_EMU_INC_STATS(cmp_sor_s);
2513 break;
2514 case 2:
2515 MIPS_FPU_EMU_INC_STATS(cmp_sune_s);
2516 break;
2517 case 3:
2518 MIPS_FPU_EMU_INC_STATS(cmp_sne_s);
2519 break;
2520 }
2521 }
2522 }
2523
2352 /* fmt is w_fmt for single precision so fix it */
2353 rfmt = s_fmt;
2354 /* default to false */
2355 rv.w = 0;
2356
2357 /* CMP.condn.S */
2358 SPFROMREG(fs, MIPSInst_FS(ir));
2359 SPFROMREG(ft, MIPSInst_FT(ir));

--- 41 unchanged lines hidden (view full) ---

2401 if (!cpu_has_mips_3_4_5_64_r2_r6)
2402 return SIGILL;
2403
2404 DIFROMREG(bits, MIPSInst_FS(ir));
2405
2406 switch (MIPSInst_FUNC(ir)) {
2407 case fcvts_op:
2408 /* convert long to single precision real */
2524 /* fmt is w_fmt for single precision so fix it */
2525 rfmt = s_fmt;
2526 /* default to false */
2527 rv.w = 0;
2528
2529 /* CMP.condn.S */
2530 SPFROMREG(fs, MIPSInst_FS(ir));
2531 SPFROMREG(ft, MIPSInst_FT(ir));

--- 41 unchanged lines hidden (view full) ---

2573 if (!cpu_has_mips_3_4_5_64_r2_r6)
2574 return SIGILL;
2575
2576 DIFROMREG(bits, MIPSInst_FS(ir));
2577
2578 switch (MIPSInst_FUNC(ir)) {
2579 case fcvts_op:
2580 /* convert long to single precision real */
2581 MIPS_FPU_EMU_INC_STATS(cvt_s_l);
2409 rv.s = ieee754sp_flong(bits);
2410 rfmt = s_fmt;
2411 goto copcsr;
2412 case fcvtd_op:
2413 /* convert long to double precision real */
2582 rv.s = ieee754sp_flong(bits);
2583 rfmt = s_fmt;
2584 goto copcsr;
2585 case fcvtd_op:
2586 /* convert long to double precision real */
2587 MIPS_FPU_EMU_INC_STATS(cvt_d_l);
2414 rv.d = ieee754dp_flong(bits);
2415 rfmt = d_fmt;
2416 goto copcsr;
2417 default: {
2418 /* Emulating the new CMP.condn.fmt R6 instruction */
2419 int cmpop = MIPSInst_FUNC(ir) & CMPOP_MASK;
2420 int sig = MIPSInst_FUNC(ir) & SIGN_BIT;
2421 union ieee754dp fs, ft;
2422
2423 if (!cpu_has_mips_r6 ||
2424 (MIPSInst_FUNC(ir) & 0x20))
2425 return SIGILL;
2426
2588 rv.d = ieee754dp_flong(bits);
2589 rfmt = d_fmt;
2590 goto copcsr;
2591 default: {
2592 /* Emulating the new CMP.condn.fmt R6 instruction */
2593 int cmpop = MIPSInst_FUNC(ir) & CMPOP_MASK;
2594 int sig = MIPSInst_FUNC(ir) & SIGN_BIT;
2595 union ieee754dp fs, ft;
2596
2597 if (!cpu_has_mips_r6 ||
2598 (MIPSInst_FUNC(ir) & 0x20))
2599 return SIGILL;
2600
2601 if (!sig) {
2602 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {
2603 switch (cmpop) {
2604 case 0:
2605 MIPS_FPU_EMU_INC_STATS(cmp_af_d);
2606 break;
2607 case 1:
2608 MIPS_FPU_EMU_INC_STATS(cmp_un_d);
2609 break;
2610 case 2:
2611 MIPS_FPU_EMU_INC_STATS(cmp_eq_d);
2612 break;
2613 case 3:
2614 MIPS_FPU_EMU_INC_STATS(cmp_ueq_d);
2615 break;
2616 case 4:
2617 MIPS_FPU_EMU_INC_STATS(cmp_lt_d);
2618 break;
2619 case 5:
2620 MIPS_FPU_EMU_INC_STATS(cmp_ult_d);
2621 break;
2622 case 6:
2623 MIPS_FPU_EMU_INC_STATS(cmp_le_d);
2624 break;
2625 case 7:
2626 MIPS_FPU_EMU_INC_STATS(cmp_ule_d);
2627 break;
2628 }
2629 } else {
2630 switch (cmpop) {
2631 case 1:
2632 MIPS_FPU_EMU_INC_STATS(cmp_or_d);
2633 break;
2634 case 2:
2635 MIPS_FPU_EMU_INC_STATS(cmp_une_d);
2636 break;
2637 case 3:
2638 MIPS_FPU_EMU_INC_STATS(cmp_ne_d);
2639 break;
2640 }
2641 }
2642 } else {
2643 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {
2644 switch (cmpop) {
2645 case 0:
2646 MIPS_FPU_EMU_INC_STATS(cmp_saf_d);
2647 break;
2648 case 1:
2649 MIPS_FPU_EMU_INC_STATS(cmp_sun_d);
2650 break;
2651 case 2:
2652 MIPS_FPU_EMU_INC_STATS(cmp_seq_d);
2653 break;
2654 case 3:
2655 MIPS_FPU_EMU_INC_STATS(cmp_sueq_d);
2656 break;
2657 case 4:
2658 MIPS_FPU_EMU_INC_STATS(cmp_slt_d);
2659 break;
2660 case 5:
2661 MIPS_FPU_EMU_INC_STATS(cmp_sult_d);
2662 break;
2663 case 6:
2664 MIPS_FPU_EMU_INC_STATS(cmp_sle_d);
2665 break;
2666 case 7:
2667 MIPS_FPU_EMU_INC_STATS(cmp_sule_d);
2668 break;
2669 }
2670 } else {
2671 switch (cmpop) {
2672 case 1:
2673 MIPS_FPU_EMU_INC_STATS(cmp_sor_d);
2674 break;
2675 case 2:
2676 MIPS_FPU_EMU_INC_STATS(cmp_sune_d);
2677 break;
2678 case 3:
2679 MIPS_FPU_EMU_INC_STATS(cmp_sne_d);
2680 break;
2681 }
2682 }
2683 }
2684
2427 /* fmt is l_fmt for double precision so fix it */
2428 rfmt = d_fmt;
2429 /* default to false */
2430 rv.l = 0;
2431
2432 /* CMP.condn.D */
2433 DPFROMREG(fs, MIPSInst_FS(ir));
2434 DPFROMREG(ft, MIPSInst_FT(ir));

--- 227 unchanged lines hidden --- 		2685 /* fmt is l_fmt for double precision so fix it */
2686 rfmt = d_fmt;
2687 /* default to false */
2688 rv.l = 0;
2689
2690 /* CMP.condn.D */
2691 DPFROMREG(fs, MIPSInst_FS(ir));
2692 DPFROMREG(ft, MIPSInst_FT(ir));

--- 227 unchanged lines hidden ---